- 1 Overview
- 2 Supported QSPI modes
- 3 Default QSPI Pin mapping
- 4 Tracing on STM32MP15x
The STM32MP15x is a heterogeneous dual-core MCU with a Cortex-M4 and one or two Cortex-A7 cores.
Supported QSPI modes
Currently, J-Link supports Dual QSPI Flash-Mode and Single QSPI Flashbank(Bank 1 or Bank2) programming.
Default QSPI Pin mapping
|Port||Pin||Pin Function||Alt Func|
WARNING: The QSPI programming in this device is done through AP - Cortex-M4. In order to allow J-Link to communicate with the Cortex-M4 AP the STM32MP1xx needs to be set in "Engineering Boot Mode".
NOTE: If you wish to use a QSPI GPIO configuration different than the default provided one, please get in contact with SEGGER Support.
Tracing on STM32MP15x
This article describes how to get started with trace on the ST STM32MP15x series. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The ST STM32MP15x series implements tracing via pins and trace buffer (TMC/ETB), so a J-Trace is only needed for stream tracing.
In order to use trace on the ST STM32MP15x series devices, the following minimum requirements have to be met:
- J-Link software version V6.60 or later
- Ozone V4.70e or later (if trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
- J-Trace PRO for Cortex-M HW version V1.0 or later / J-Link Plus version V10 or later for TMC/ETB
- For access to the trace pins on the eval board the J-Trace Mictor adapter has been used
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a STM32MP15X-EVAL. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Note: The example is shipped with a compiled .JLinkScriptfile (.pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following project as reference: Tracing on SEGGER_Cortex-M_Trace_Reference_Board
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate ETB trace on the Cortex-M4 core. The project has been tested with the minimum requirements mentioned above and a STM32MP15X-EVAL. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Note: ETB does not support streaming trace features.
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.