NXP i.MX 8
The NXP i.MX 8 are embedded multi-core processors consisting of two Cortex-M4, four Cortex-A53 and two Cortex-A72.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Watchdog Handling
System controller firmware handles watchdog during boot and programming of boot devices.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8 family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| 2 x Cortex-A72 | 
|
| 4 x Cortex-A53 |
|
| 2 x Cortex-M4F | 
|
| 1 x HIFI4 DSP |
|
The i.MX 8 family processors have additional cores:
- System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration.
- Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M4F core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Device Specific Handling
Connect
Debugging of Cortex-M4 cores is enabled after primary boot stage. A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target.
Reset
J-Link does not support reset of particular cores, as it is controlled by SCU.
