NXP i.MX 8M Plus
The NXP i.MX 8M Plus are embedded multi-core processors consisting of one Cortex-M7, up to four Cortex-A53 and one Tensilica HiFi 4 DSP.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8M Plus family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| 4 x Cortex-A53 | 
|
| 1 x Cortex-M7 |
|
| 1 x HIFI4 DSP | 
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A53 core(s)
Init/Setup
The core(s) are enabled after boot.
Reset
Core reset is not performed.
Attach
Attach is supported.
Cortex-M7 core(s)
Init/Setup
The core(s) are enabled after boot. During connect the M7 is set to execute an endless loop at 0x00000000 (TCM RAM).
Reset
Reset is performed by using device-specific registers, than target CPU is halted.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions.
Device Specific Handling
Connect
After the boot stage J-Link writes an "infinite loop" code to the start of the M7s TCM RAM. After the boot stage J-Link can be attached to a running target. By default only the main A53 core is enable, the other cores can be enabled by the bootloader or operating system kernel. In order to have read/write accesse to system memory, MMU should be configured accordingly.
