Latest revision as of 11:08, 16 May 2024

The Codasip L10 is a 32-bit (RV32) core, designed by Codasip.

Minimum required J-Link software version

The L10 device selection is supported since V7.24 of the J-Link software.

RTT is automatically supported by J-Link if the core supports system bus access (SBA)
As SBA is a configuration option of the core, the configuration option must be chosen to have RTT support

See RTT.

Revision as of 10:19, 15 June 2021 (view source) Alex (talk \| contribs) ← Older edit		Latest revision as of 11:08, 16 May 2024 (view source) Simon Buchholz (talk \| contribs)
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	The Codasip L10 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip].		The Codasip L10 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip].