Difference between revisions of "NXP MCXA18"
(Created page with "The '''NXP MCXA18''' are single core ARM Cortex-M33 microprocessors. __TOC__ ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! Flash Bank || Base address !! Si...") |
(Redirected page to NXP MCXA) (Tag: New redirect) |
||
(3 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
+ | #REDIRECT [[NXP_MCXA]] |
||
− | The '''NXP MCXA18''' are single core ARM Cortex-M33 microprocessors. |
||
− | __TOC__ |
||
− | |||
− | ==Flash Banks== |
||
− | ===Internal Flash=== |
||
− | {| class="seggertable" |
||
− | |- |
||
− | ! Flash Bank || Base address !! Size || J-Link Support |
||
− | |- |
||
− | | Internal Flash || 0x00000000 || up to 1024 KB || style="text-align:center;"| {{YES}} |
||
− | |} |
||
− | |||
− | ====ECC Flash ==== |
||
− | *Device has ECC Flash, but no special handling required. |
||
− | |||
− | ==ECC RAM == |
||
− | *Device has 8KB ECC RAM named SRAM A0, can be used when LPCAC is switched off |
||
− | |||
− | ==Watchdog Handling== |
||
− | *The device has 2 watchdogs WWDT and CDOG. |
||
− | *The watchdog WWDT is fed during flash programming. |
||
− | *No handling for CDOG implemented. |
||
− | |||
− | ==Device Specific Handling== |
||
− | |||
− | ===Reset=== |
||
− | *The J-Link performs a device specific reset sequence. SRAM and Flash is set to RWX. |
||
− | |||
− | ===Attach=== |
||
− | Attach is supported. |
||
− | |||
− | ==Evaluation Boards== |
||
− | [[NXP_MCX-A14X-EVK|NXP MCX-A14X-EVK evaluation board]] |
||
− | |||
− | ==Example Application== |
||
− | [[NXP_MCX-A14X-EVK#Example_Project|NXP MCX-A14X-EVK evaluation board]] |
Latest revision as of 12:38, 27 May 2024
Redirect to: