Infineon PMG1
The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | Up to 256 KB | 
|
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Device Specific Handling
Connect
The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:
- Reset mode:
J-Link toggles the XRES line and then sends SWD commands.
Reset mode is not supported by EZ-PD™ PMG1-S0 MCU devices because they do not have an XRES pin.
- Power Cycle mode:
J-Link powers on the target and then starts sending the SWD commands.
This is the only mode supported by EZ-PD™ PMG1-S0 MCU devices.
Reset
- The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry pioint
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
Evaluation Boards
Example Application
Tracing
The following trace example projects are available:
- [Link to Board Article1]
- [Link to Board Article2]
- ...
