Difference between revisions of "XHSC HC32L19x"
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[[Category:Device families]] |
[[Category:Device families]] |
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| − | The '''XHSC HC32L19x''' are |
+ | The '''XHSC HC32L19x''' are Cortex-M0+ based micro controllers. |
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==Device Specific Handling== |
==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| + | *[[XHSC_HC32LF17/9xGO-STK-V2.0|XHSC HC32LF17/9xGO-STK-V2.0]] |
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| − | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[XHSC_HC32LF17/9xGO-STK-V2.0#Example_Project |XHSC HC32LF17/9xGO-STK-V2.0]] |
Latest revision as of 19:22, 17 June 2024
The XHSC HC32L19x are Cortex-M0+ based micro controllers.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | 256 KB | 
|
Watchdog Handling
- The device has a watchdog [WDT].
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
