XHSC HC32L19x
Revision as of 19:07, 17 June 2024 by Torben.scharping (talk | contribs) (Created page with "Category:Device families The '''XHSC HC32L19x''' are [SHORT_DESCRIPTION] __TOC__ ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! Flash Bank !! Base addre...")
The XHSC HC32L19x are [SHORT_DESCRIPTION]
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00000000 | 256 KB | ![]() |
Watchdog Handling
- The device has a watchdog [WDT].
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.