Difference between revisions of "XHSC HC32LF17/9xGO-STK-V2.0"
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This article describes specifics for the XHSC HC32LF17/9xGO-STK-V2.0 evaluation board.<br> |
This article describes specifics for the XHSC HC32LF17/9xGO-STK-V2.0 evaluation board.<br> |
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| − | '''[PICTURE OF BOARD]''' |
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[[File:XHSC_HC32LF17-9x GO-STK-V2.0_HC32L196PCTA_board.jpg|450px]] |
[[File:XHSC_HC32LF17-9x GO-STK-V2.0_HC32L196PCTA_board.jpg|450px]] |
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== Preparing for J-Link == |
== Preparing for J-Link == |
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| − | *Connect the J-Link to ...... |
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*Connect the J-Link to this pins: |
*Connect the J-Link to this pins: |
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{| class="seggertable" |
{| class="seggertable" |
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Latest revision as of 19:19, 17 June 2024
This article describes specifics for the XHSC HC32LF17/9xGO-STK-V2.0 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | CN5 | 1 | VDD |
| GND | CN5 | 4 | GND |
| nTRST | CN5 | 6 | RSTB |
| TMS/SWDIO | CN5 | 3 | SWIO |
| TCK/SWCLK | CN5 | 2 | SWCK |
- Power the board via CN6.
- The debugger CMSIS-DAP-V1.0 has to be removed.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the XHSC HC32LF17/9xGO-STK-V2.0.
It is a simple Hello World sample linked into the internal flash.
SETUP
- Embedded Studio: V7.20
- Hardware: XHSC HC32LF17/9xGO-STK-V2.0
- Link: File:XHSC HC32L196PCTA TestProject ES V720.zip
