Difference between revisions of "GigaDevice GD32A4"
(→Internal Flash) |
|||
| Line 18: | Line 18: | ||
| OTP Bytes || 0x1FFF7800 || 512 B || style="text-align:center;"| {{NO}} |
| OTP Bytes || 0x1FFF7800 || 512 B || style="text-align:center;"| {{NO}} |
||
|} |
|} |
||
| − | |||
| − | ==ECC RAM== |
||
| − | In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
||
| − | starting at 0x2000 0000. |
||
==Watchdog Handling== |
==Watchdog Handling== |
||
| Line 35: | Line 31: | ||
==Evaluation Boards== |
==Evaluation Boards== |
||
| − | *[[ |
+ | *[[GigaDevice_GD32A490I-EVAL|GigaDevice GD32A490I-EVAL]] |
==Example Application== |
==Example Application== |
||
| − | *[[ |
+ | *[[GigaDevice_GD32A490I-EVAL#Example_Project | GigaDevice GD32A490I-EVAL]] |
Latest revision as of 08:39, 25 June 2024
The GD32A49x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M4 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 3 MB | 
|
| Option Byte Bank 0 | 0x1FFFC000 | 16 B | 
|
| Option Byte Bank 1 | 0x1FFEC000 | 16 B |
|
| OTP Bytes | 0x1FFF7800 | 512 B |
|
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
