Difference between revisions of "GigaDevice GD32F5"
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| Option Bytes (Bank 1) || 0x1FFEC000 || 16 B || style="text-align:center;"| {{NO}} |
| Option Bytes (Bank 1) || 0x1FFEC000 || 16 B || style="text-align:center;"| {{NO}} |
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| + | ==ECC RAM== |
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| + | In order to prevent errors when reading first time, the DLL initializes the first 256KB of RAM |
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| + | starting at 0x2000 0000. |
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==Watchdog Handling== |
==Watchdog Handling== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[ |
+ | *[[GigaDevice_GD32F527I-EVAL | GigaDevice GD32F527I-EVAL]] |
| − | *[[GigaDevice_GD32407H-START | GigaDevice GD32407H-START]] |
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| − | *[[GigaDevice_GD32407V-START | GigaDevice GD32407V-START]] |
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| − | *[[GigaDevice_GD32450I-EVAL | GigaDevice GD32450I-EVAL]] |
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| − | *[[GigaDevice_GD32450Z-EVAL | GigaDevice GD32450Z-EVAL]] |
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| − | *[[GigaDevice_GD32F427V-START | GigaDevice GD32F427V-START]] |
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| − | *[[GigaDevice_GD32F470Z-EVAL | GigaDevice GD32F470Z-EVAL]] |
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==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[GigaDevice_GD32F527I-EVAL#Example_Project | GigaDevice GD32F527I-EVAL]] |
| − | *[[GigaDevice_GD32407H-START#Example_Project | GigaDevice GD32407H-START]] |
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| − | *[[GigaDevice_GD32407V-START#Example_Project | GigaDevice GD32407V-START]] |
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| − | *[[GigaDevice_GD32450I-EVAL#Example_Project | GigaDevice GD32450I-EVAL]] |
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| − | *[[GigaDevice_GD32450Z-EVAL#Example_Project | GigaDevice GD32450Z-EVAL]] |
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| − | *[[GigaDevice_GD32F427V-START#Example_Project | GigaDevice GD32F427V-START]] |
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| − | *[[GigaDevice_GD32F470Z-EVAL#Example_Project | GigaDevice GD32F470Z-EVAL]] |
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Latest revision as of 09:07, 25 June 2024
The GigaDevice GD32F5 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M33 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 3072 KB | 
|
| OTP Block 1 (data) | 0x1FF00000 | 8 KB | 
|
| OTP Block 2 (data) | 0x1FF20000 | 512 B |
|
| OTP Block 1 (lock) | 0x1FF20200 | 16 B |
|
| OTP Block 2 (lock) | 0x1FF20210 | 16 B |
|
| OTP0 Block (data) | 0x1FFF7800 | 64 B |
|
| OTP0 Block (lock) | 0x1FFF7840 | 16 B |
|
| Option Bytes (Bank 0) | 0x1FFFC000 | 16 B |
|
| Option Bytes (Bank 1) | 0x1FFEC000 | 16 B |
|
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 256KB of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs, FWDGT and WWDGT.
- The WWDGT watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
