Difference between revisions of "e-peas EDMS105N EVK"
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== Preparing for J-Link == |
== Preparing for J-Link == |
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| − | *Connect the J-Link to |
+ | *Connect the J-Link to the following Pins: |
| + | ** GND: CN4.1 |
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| − | *Power the board via........ |
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| + | ** VTref: CN5.1 |
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| + | ** SWDIO: JP7.3 |
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| + | ** SWCLK_ JP7.1 |
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| + | ** RESET: JP7.5 |
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| + | *Power the board via S1. |
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* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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[[File:Epeas_MDNS105N-xxyP_connect.png|400px]] |
[[File:Epeas_MDNS105N-xxyP_connect.png|400px]] |
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Revision as of 16:05, 29 June 2023
This article describes specifics for the e-peas EDMS105N_EVK evaluation board.
[PICTURE OF BOARD]
450px
Preparing for J-Link
- Connect the J-Link to the following Pins:
- GND: CN4.1
- VTref: CN5.1
- SWDIO: JP7.3
- SWCLK_ JP7.1
- RESET: JP7.5
- Power the board via S1.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the e-peas EDMS105N_EVK.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.88k
- Embedded Studio: V6.34
- Hardware: e-peas EDMS105N_EVK
- Link: File:Epeas EDMS105N TestProject ES V634.zip
