Difference between revisions of "Template:JLinkResetStrategiesCortexAR"
| Line 1: | Line 1: | ||
| − | J-Link supports a default reset strategy for the {{1}} cores. |
+ | J-Link supports a default reset strategy for the {{{1}}} cores. |
The following reset strategy is available via JTAG and in SWD as target interface. |
The following reset strategy is available via JTAG and in SWD as target interface. |
||
It halts the CPU after the reset. |
It halts the CPU after the reset. |
||
Latest revision as of 11:52, 7 August 2023
J-Link supports a default reset strategy for the {{{1}}} cores. The following reset strategy is available via JTAG and in SWD as target interface. It halts the CPU after the reset.
Note:
It is recommended that the correct device is selected in the debugger so the debugger can pass the device name to the J-Link Software which makes it possible for J-Link to detect what is the best reset strategy for the device.
Type 0: Normal
J-Link sets vector catch enable in Vector Catch Register and DBGNOPWRDWN in Device Power Down and Reset Control Register. Afterwards reset is triggered via reset pin with a (by default) 20ms high phase. After the reset signal J-Link waits 100ms delay to let the core boot.
