Difference between revisions of "NXP PN7462"
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==Device Specific Handling== |
==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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*The device uses custom reset which halts the CPU after Boot ROM execution. |
*The device uses custom reset which halts the CPU after Boot ROM execution. |
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===Attach=== |
===Attach=== |
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| − | Attach is |
+ | Attach is supported. |
==Evaluation Boards== |
==Evaluation Boards== |
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| − | * |
+ | *NXP PN640 Performance evaluation board: http://wiki.segger.com/NXP_PN640_Perf_Board |
==Example Application== |
==Example Application== |
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| − | * |
+ | *NXP PN640 Performance evaluation board: http://wiki.segger.com/NXP_PN640_Perf_Board#Example_Project |
| − | > |
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Revision as of 14:56, 20 September 2023
The NXP PN7462 family is a family of 32-bit Arm Cortex-M0-based NFC microcontrollers offering high performance and low power consumption.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00203000 | Up to 158 KB | 
|
| EEPROM | 0x00201200 | 3584 B |
|
Watchdog Handling
- The device has a watchdog timer [WDT].
- The watchdog is not fed during flash programming.
Device Specific Handling
Reset
- The device uses custom reset which halts the CPU after Boot ROM execution.
Attach
Attach is supported.
Evaluation Boards
- NXP PN640 Performance evaluation board: http://wiki.segger.com/NXP_PN640_Perf_Board
Example Application
- NXP PN640 Performance evaluation board: http://wiki.segger.com/NXP_PN640_Perf_Board#Example_Project
