Difference between revisions of "Infineon PMG1"
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*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | {| class="seggertable" |
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| − | |- |
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| − | ! Core || J-Link Support |
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| − | |- |
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| − | | [CORE_NAME] || style="text-align:center;"| {{YES}} / {{NO}} |
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| − | |} |
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| − | |||
| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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Revision as of 10:49, 13 May 2024
The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | Up to 256 KB | 
|
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
- The device uses Cortex-M Core reset, no special handling necessary, like described here.
- The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses Cortex-A reset, no special handling necessary, like described here.
- The device uses Cortex-R reset, no special handling necessary, like described here.
- The device uses ARMv8-A reset, no special handling necessary, like described here.
- The device uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
Evaluation Boards
Example Application
Tracing
The following trace example projects are available:
- [Link to Board Article1]
- [Link to Board Article2]
- ...
