Difference between revisions of "NXP RD-RW616-BGA IPA-2A/1A"

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(Created page with "__TOC__ This article describes specifics for the NXP RD-RW616-BGA_IPA-2A/1A evaluation board.<br> '''[PICTURE OF BOARD]''' 450px == Preparing f...")
 
 
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[[Category:Evalboards]]
 
__TOC__
  
__TOC__
   
 
This article describes specifics for the NXP RD-RW616-BGA_IPA-2A/1A evaluation board.<br>
  
This article describes specifics for the NXP RD-RW616-BGA_IPA-2A/1A evaluation board.<br>
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[[File:NXP_RD-RW612-BGA_RW612EV_board.jpg|450px]]
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'''[PICTURE OF BOARD]'''
  
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[[File:VENDOR_BOARDNAME.jpg|450px]]
  
   
 
== Preparing for J-Link ==
  
== Preparing for J-Link ==
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*Connect the J-Link to ......
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* Power the board via J1
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* Jumper JP1 must be set in order to use J-Link
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*Power the board via........
  
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'''For use of SWD:'''
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** HD12 1-2 has to be closed (RF_CNTL_2/CON[11])
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** Connect JLINK to P2 (SWD)
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'''For use of JTAG:'''
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** HD12 1-2 has to be open (RF_CNTL_2/CON[11])
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** Connect JLINK to J19 (JTAG)
 
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
  
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
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[[File:NXP_RD-RW612-BGA_RW612EV_connect.png|400px]]
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'''[PICTURE OF CONNECT]'''
  
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[[File:VENDOR_DEVICE_CONNECT.PNG|400px]]
  
   
 
== Example Project==
  
== Example Project==
 
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the NXP RD-RW616-BGA_IPA-2A/1A.<br>It is a simple Hello World sample linked into the internal flash.<br>
  
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the NXP RD-RW616-BGA_IPA-2A/1A.<br>It is a simple Hello World sample linked into the internal flash.<br>
 
====SETUP====
  
====SETUP====
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*J-Link software: V6.74
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*J-Link software: V7.92c
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*Embedded Studio: V4.52b
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*Embedded Studio: V7.20
 
*Hardware: NXP RD-RW616-BGA_IPA-2A/1A
  
*Hardware: NXP RD-RW616-BGA_IPA-2A/1A
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*Link: [[File:VENDOR_DEVICENAME_TestProject_ES_V452b.zip]]
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*Link: [[File:NXP_RW61x_TestProject_ES_7V20.zip]]

Latest revision as of 13:20, 15 May 2024

This article describes specifics for the NXP RD-RW616-BGA_IPA-2A/1A evaluation board.
NXP RD-RW612-BGA RW612EV board.jpg

Preparing for J-Link

  • Power the board via J1
  • Jumper JP1 must be set in order to use J-Link

For use of SWD:

    • HD12 1-2 has to be closed (RF_CNTL_2/CON[11])
    • Connect JLINK to P2 (SWD)

For use of JTAG:

    • HD12 1-2 has to be open (RF_CNTL_2/CON[11])
    • Connect JLINK to J19 (JTAG)
  • Verify the Connection with e.g. J-Link Commander. The output should look as follows:

NXP RD-RW612-BGA RW612EV connect.png

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the NXP RD-RW616-BGA_IPA-2A/1A.
It is a simple Hello World sample linked into the internal flash.

SETUP

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