Difference between revisions of "Infineon WLC"
(Created page with "Category:Device families The '''Infineon PMG1''' is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU. __TOC__ ==Flash Banks== ===Internal Flash=...") |
|||
| (4 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
[[Category:Device families]] |
[[Category:Device families]] |
||
| − | The '''Infineon |
+ | The '''Infineon WLC''' is a family of wireless charging transmitter ICs with Arm® Cortex®-M0 CPU. |
__TOC__ |
__TOC__ |
||
| Line 7: | Line 7: | ||
{| class="seggertable" |
{| class="seggertable" |
||
|- |
|- |
||
| − | ! |
+ | ! Flash Bank || Base address !! Size || J-Link Support |
|- |
|- |
||
| − | + | | Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
|
| − | |- |
||
| − | | PMG1-S0 || CYPM1011 || Internal Flash || 0x00000000 || 64 KB || style="text-align:center;"| {{YES}} |
||
| − | |- |
||
| − | | PMG1-S1 || CYPM1111 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
||
| − | |- |
||
| − | | PMG1-S2 || CYPM1211 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
||
| − | |- |
||
| − | | PMG1-S3 || CYPM1311 || Internal Flash || 0x00000000 || 256 KB || style="text-align:center;"| {{YES}} |
||
|} |
|} |
||
| Line 26: | Line 18: | ||
==Device Specific Handling== |
==Device Specific Handling== |
||
===Connect=== |
===Connect=== |
||
| − | The connect sequence |
+ | The connect sequence WLC devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:<br> |
| + | * Reset mode: <br> |
||
| − | * Reset mode: <br> J-Link toggles the XRES line and then sends SWD commands.<br>Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.<br> |
||
| + | J-Link toggles the XRES line and then sends SWD commands.<br> |
||
| − | * Power Cycle mode:<br> J-Link powers on the target and then starts sending the SWD commands.<br>Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br>Make sure to set VSupply (pin 19) correctly before connecting it to the target board.<br>This is the only mode supported by PMG1-S0 devices.<br> |
||
| + | * Power Cycle mode:<br> |
||
| + | J-Link powers on the target and then starts sending the SWD commands.<br> |
||
| + | Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br> |
||
| + | Make sure to set VSupply (pin 19) correctly before connecting it to the target board.<br> |
||
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br> |
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br> |
||
| Line 39: | Line 35: | ||
==Evaluation Boards== |
==Evaluation Boards== |
||
| + | *[[Infineon_REF_WLC_TX15W_C1| WLC_TX15W_C1]] |
||
| − | *[[Infineon_EVAL_PMG1_B1_DRP| EVAL_PMG1_B1_DRP]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
||
| − | |||
==Example Application== |
==Example Application== |
||
| + | *[[Infineon_REF_WLC_TX15W_C1| WLC_TX15W_C1]] |
||
| − | *[[Infineon_EVAL_PMG1_B1_DRP#Example_Project | EVAL_PMG1_B1_DRP]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
||
| − | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
||
Latest revision as of 10:33, 30 May 2024
The Infineon WLC is a family of wireless charging transmitter ICs with Arm® Cortex®-M0 CPU.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | 128 KB | 
|
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog is not fed during flash programming.
Device Specific Handling
Connect
The connect sequence WLC devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:
- Reset mode:
J-Link toggles the XRES line and then sends SWD commands.
- Power Cycle mode:
J-Link powers on the target and then starts sending the SWD commands.
Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.
Make sure to set VSupply (pin 19) correctly before connecting it to the target board.
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.
Reset
- The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point.
Limitations
Attach
Attach is not supported because the J-Link resets the device on connect.
