Difference between revisions of "GigaDevice GD32L235"
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| OTP Bytes || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}} |
| OTP Bytes || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}} |
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| + | ==ECC RAM == |
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| + | *Device has ECC/Parity RAM. |
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| + | *RAM is initialized on connect. |
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==Watchdog Handling== |
==Watchdog Handling== |
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*The device does have 2 watchdogs, FWDGT and WWDGT. |
*The device does have 2 watchdogs, FWDGT and WWDGT. |
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| − | *The |
+ | *The FWDGT watchdog is fed during flash programming. |
| + | *The WWDGT watchdog is fed only when activated during flash programming. |
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==Device Specific Handling== |
==Device Specific Handling== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[ |
+ | *[[GigaDevice_GD32L235R-EVAL | GigaDevice GD32L235R-EVAL]] |
| − | *[[GigaDevice_GD32L233R-EVAL | GigaDevice GD32L233R-EVAL]] |
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==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[GigaDevice_GD32L235R-EVAL#Example_Project | GigaDevice GD32L235R-EVAL]] |
| − | *[[GigaDevice_GD32L233R-EVAL#Example_Project | GigaDevice GD32L233R-EVAL]] |
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Latest revision as of 13:30, 13 June 2024
The GigaDevice GD32L235 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M23 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 128 KB | 
|
| Option Bytes | 0x1FFFF800 | 16 B |
|
| OTP Bytes | 0x1FFF7000 | 512 B | 
|
ECC RAM
- Device has ECC/Parity RAM.
- RAM is initialized on connect.
Watchdog Handling
- The device does have 2 watchdogs, FWDGT and WWDGT.
- The FWDGT watchdog is fed during flash programming.
- The WWDGT watchdog is fed only when activated during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
