Difference between revisions of "RZ A1L"
(Created page with "__TOC__ The Renesas RZ/A1L is a high-end 32-bit CPU, based on the Cortex-A9 core. = QSPI Flash Programming Support = QSPI Flash programming support is provided through the...") |
(→Quad-SPI Interface Pins) |
||
Line 25: | Line 25: | ||
|} |
|} |
||
+ | |||
− | ====Quad-SPI Interface Pins==== |
||
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI: |
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI: |
||
{| class="wikitable" |
{| class="wikitable" |
Revision as of 10:19, 17 June 2020
Contents
The Renesas RZ/A1L is a high-end 32-bit CPU, based on the Cortex-A9 core.
QSPI Flash Programming Support
QSPI Flash programming support is provided through the following pin configs:
Quad-SPI Interface Pins
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:
Alternate function | Port / Pin |
---|---|
SPBCLK_0 | P4_4 |
SPBSSL_0 | P4_5 |
SPIO00 | P4_6 |
SPIO10 | P4_7 |
SPIO20 | P4_2 |
SPIO30 | P4_3 |
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:
Alternate function | Port / Pin |
---|---|
SPIO01 | P3_10 |
SPIO11 | P3_11 |
SPIO21 | P3_12 |
SPIO31 | P3_13 |
Programming external parallel CFI NOR flash
TBD.