Difference between revisions of "J-Trace PRO Cortex V3"
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− | == Hardware |
+ | == Hardware Features == |
− | {| class=" |
+ | {| class="seggertable" |
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+ | ! Feature !! Supported |
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− | ! style="position:sticky; top:0"|Hardware version |
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− | ! style="position:sticky; top:0"|3 |
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− | |- style="text-align:center" |
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− | |colspan="7"| Hardware Features |
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− | + | | USB 2.0 Hi-Speed ||style="text-align:center;"| {{YES}} |
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− | + | | USB 3.0 SuperSpeed ||style="text-align:center;"| {{YES}} |
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− | + | | WinUSB ||style="text-align:center;"| {{YES}} |
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− | + | | Gigabit-Ethernet ||style="text-align:center;"| {{YES}} |
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− | + | | cJTAG interface ||style="text-align:center;"| {{YES}} |
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− | + | | cJTAG interface without/buggy KEEPER logic ||style="text-align:center;"| {{YES}} |
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− | + | | JTAG interface ||style="text-align:center;"| {{YES}} |
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− | + | | SWD interface ||style="text-align:center;"| {{YES}} |
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− | + | | SWO interface ||style="text-align:center;"| {{YES}} |
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− | + | | ETB Trace Cortex ||style="text-align:center;"| {{YES}} |
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− | + | | ETM Trace Cortex ||style="text-align:center;"| {{YES}} |
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− | + | | PTM Trace Cortex ||style="text-align:center;"| {{YES}} |
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− | + | | Streaming Trace ||style="text-align:center;"| {{YES}} |
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− | + | | VCOM ||style="text-align:center;"| {{NO}} |
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− | + | | Memory Stop mode support ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{YES}} |
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− | + | | 5 V Target Supply ||style="text-align:center;"| {{YES}} |
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− | + | | SWD Multi-Drop ||style="text-align:center;"| {{YES}} |
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− | |- style="text-align:center" |
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− | |colspan="7"| ARM Cortex Cores |
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− | + | | CMSIS-DAP mode ||style="text-align:center;"| {{NO}} |
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+ | |} |
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+ | |||
+ | == Supported cores == |
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+ | J-Trace provides debugging support for the following cores.<br> |
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+ | {{Note|1=If you are interested in j-Trace support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}} |
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+ | |||
+ | {| class="seggertable" |
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+ | ! Core !! Supported |
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− | ! style="text-align:left;"|Cortex-A7 || {{YES}} |
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− | ! |
+ | !colspan="2"| ARM Cortex Cores |
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− | + | | Cortex-A5 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A7 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A8 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A9 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A12 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A15 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A17 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A53 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A55 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A57 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A72 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-R4 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-R5 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-R8 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M0 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M0+ ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M1 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M3 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M4 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M7 ||style="text-align:center;"| {{YES}} |
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− | |- style="text-align:center" |
+ | | Cortex-M23 ||style="text-align:center;"| {{YES}} |
− | |colspan="7"| RISC-V |
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− | + | | Cortex-M33 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M85 ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | | SC000 (M0 secure) ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | | SC300 (M3 secure) ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | !colspan="2"| RISC-V |
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+ | |- |
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+ | | RV32 ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | | RV64 ||style="text-align:center;"| {{NO}} |
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Latest revision as of 16:26, 20 December 2022
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Trace PRO for Cortex V3.
Contents
Hardware Features
Feature | Supported |
---|---|
USB 2.0 Hi-Speed | |
USB 3.0 SuperSpeed | |
WinUSB | |
Gigabit-Ethernet | |
cJTAG interface | |
cJTAG interface without/buggy KEEPER logic | |
JTAG interface | |
SWD interface | |
SWO interface | |
ETB Trace Cortex | |
ETM Trace Cortex | |
PTM Trace Cortex | |
Streaming Trace | |
VCOM | |
Memory Stop mode support | |
Cortex-M Monitor Mode debugging | |
5 V Target Supply | |
SWD Multi-Drop | |
CMSIS-DAP mode |
Supported cores
J-Trace provides debugging support for the following cores.
Note:
If you are interested in j-Trace support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
If you are interested in j-Trace support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core | Supported |
---|---|
ARM Cortex Cores | |
Cortex-A5 | |
Cortex-A7 | |
Cortex-A8 | |
Cortex-A9 | |
Cortex-A12 | |
Cortex-A15 | |
Cortex-A17 | |
Cortex-A53 | |
Cortex-A55 | |
Cortex-A57 | |
Cortex-A72 | |
Cortex-R4 | |
Cortex-R5 | |
Cortex-R8 | |
Cortex-M0 | |
Cortex-M0+ | |
Cortex-M1 | |
Cortex-M3 | |
Cortex-M4 | |
Cortex-M7 | |
Cortex-M23 | |
Cortex-M33 | |
Cortex-M85 | |
SC000 (M0 secure) | |
SC300 (M3 secure) | |
RISC-V | |
RV32 | |
RV64 |