Difference between revisions of "NXP MCXN11"
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| + | #Redirect[[NXP_MCXN]] |
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| − | The '''NXP MCXN11''' are single core Arm Cortex-M33 microprocessors. |
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| − | ==Flash Banks== |
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| − | ===Internal Flash=== |
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| − | {| class="seggertable" |
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| − | |- |
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| − | ! Flash Bank || Base address !! Size || J-Link Support |
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| − | |- |
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| − | | Main flash (NS) || 0x00000000 || Up to 2 MB || style="text-align:center;"| {{YES}} |
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| − | |- |
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| − | | Main flash (S) || 0x10000000 || Up to 2 MB || style="text-align:center;"| {{YES}} |
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| − | |} |
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| − | ==ECC RAM== |
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| − | *Device has ECC RAM with various settings. |
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| − | ==Device Specific Handling== |
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| − | ====Init/Setup==== |
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| − | *64KB RAMC @ 0x20010000 is used, if it set to ECC_ENABLE, it is initialized. |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported if RAMC is not set to ECC_ENABLE. |
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| − | ==Evaluation Boards== |
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| − | *[[NXP_FRDM-MCXN236|NXP FRDM-MCXN236 evaluation board]] |
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| − | ==Example Application== |
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| − | *[[NXP_FRDM-MCXN236#Example_Project|NXP FRDM-MCXN236 evaluation board]] |
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Latest revision as of 12:48, 27 May 2024
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