Difference between revisions of "NXP i.MX 8X"
(Created page with "__TOC__ The '''NXP i.MX 8X''' is an embedded multi-core processor consisting of one Cortex-M4, four Cortex-A35. == Debugging == J-Link supports debugging for the Cortex-M4....") |
|||
(4 intermediate revisions by one other user not shown) | |||
Line 1: | Line 1: | ||
+ | [[Category:Device families]] |
||
+ | The '''NXP i.MX 8X''' are embedded multi-core processors consisting of one Cortex-M4, up to two Cortex-A53 and one Tensilica HiFi 4 DSP. |
||
__TOC__ |
__TOC__ |
||
+ | ==External Boot Devices== |
||
− | The '''NXP i.MX 8X''' is an embedded multi-core processor consisting of one Cortex-M4, four Cortex-A35. |
||
+ | Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface. |
||
− | == |
+ | ==Watchdog Handling== |
+ | System controller firmware handles watchdog during boot and programming of boot devices. |
||
− | J-Link supports debugging for the Cortex-M4. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCML RAM) and afterwards halted. |
||
− | == |
+ | ==Multi-Core Support== |
+ | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
||
− | J-Link currently does not support device reset. |
||
+ | The i.MX 8X family comes with a variety of multi-core options listed in the following table:<br> |
||
+ | {| class="seggertable" |
||
+ | |- |
||
+ | ! Core || J-Link Support |
||
+ | |- |
||
+ | | 4 x Cortex-A35 ||style="text-align:center;"| {{NO}} |
||
+ | |- |
||
+ | | 1 x Cortex-M4F ||style="text-align:center;"| {{YES}} |
||
+ | |- |
||
+ | | 1 x HIFI4 DSP ||style="text-align:center;"| {{NO}} |
||
+ | |- |
||
+ | |} |
||
+ | The i.MX 8X family processors have additional cores: |
||
+ | *System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration. |
||
+ | *Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions. |
||
+ | |||
+ | In below, the debug related multi-core behavior of the J-Link is described for each core: |
||
+ | ===Cortex-A35 core(s)=== |
||
+ | ====Init/Setup==== |
||
+ | The core(s) are enabled by SCU after boot. |
||
+ | ====Reset==== |
||
+ | Core reset is performed by SCU. |
||
+ | ====Attach==== |
||
+ | Attach is supported. |
||
+ | |||
+ | ===Cortex-M4F core(s)=== |
||
+ | ====Init/Setup==== |
||
+ | The core(s) are enabled by SCU after boot. |
||
+ | ====Reset==== |
||
+ | Core reset is performed by SCU. |
||
+ | ====Attach==== |
||
+ | Attach is supported. |
||
+ | |||
+ | ==Device Specific Handling== |
||
+ | ===Connect=== |
||
+ | A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target. |
||
+ | By default only the main A35 core is enable, the other cores can be enabled by the bootloader or operating system kernel. |
||
+ | In order to have read/write accesse to system memory, MMU should be configured accordingly. |
||
+ | ===Reset=== |
||
+ | J-Link does not support reset of particular cores, as it is controlled by SCU. |
||
+ | |||
+ | ==Evaluation Boards== |
||
+ | *[[NXP_MCIMX8QXP-CPU | MCIMX8QXP-CPU]] |
||
+ | |||
+ | ==Example Application== |
||
+ | *[[File:NXP_MCIMX8QXP-CPU_M4_TestProject_ES_8V10.zip]] |
Latest revision as of 13:07, 15 May 2024
The NXP i.MX 8X are embedded multi-core processors consisting of one Cortex-M4, up to two Cortex-A53 and one Tensilica HiFi 4 DSP.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Watchdog Handling
System controller firmware handles watchdog during boot and programming of boot devices.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8X family comes with a variety of multi-core options listed in the following table:
Core | J-Link Support |
---|---|
4 x Cortex-A35 | |
1 x Cortex-M4F | |
1 x HIFI4 DSP |
The i.MX 8X family processors have additional cores:
- System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration.
- Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A35 core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Cortex-M4F core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Device Specific Handling
Connect
A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target. By default only the main A35 core is enable, the other cores can be enabled by the bootloader or operating system kernel. In order to have read/write accesse to system memory, MMU should be configured accordingly.
Reset
J-Link does not support reset of particular cores, as it is controlled by SCU.