Difference between revisions of "embOS MPU on CortexM"
m (Alex moved page EmbOS:MPU on CortexM to embOS:MPU on CortexM) |
m (→ARMv7-M Memory Attributes) |
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With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. |
With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. |
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− | A memory region can be added with OS_MPU_AddRegion(). |
+ | A memory region can be added with ''OS_MPU_AddRegion()''. |
+ | __TOC__ |
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− | '''OS_MPU_AddRegion() prototype:''' |
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+ | === OS_MPU_AddRegion() === |
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− | <nowiki> |
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+ | ''OS_MPU_AddRegion()'' has the following prototype: |
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+ | |||
+ | <source lang="C"> |
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void OS_MPU_AddRegion(OS_TASK* pTask, |
void OS_MPU_AddRegion(OS_TASK* pTask, |
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OS_U32 BaseAddr, |
OS_U32 BaseAddr, |
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Line 10: | Line 13: | ||
OS_U32 Permissions, |
OS_U32 Permissions, |
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OS_U32 Attributes); |
OS_U32 Attributes); |
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− | </ |
+ | </source> |
+ | === ARMv7-M Memory Attributes === |
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− | embOS-MPU includes defines for the permissions like ''OS_MPU_READONLY'' but not for the attributes since they are core specific. |
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+ | embOS-MPU includes defines for the permissions (e.g. ''OS_MPU_READONLY''), but not for the attributes since they are core specific. |
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− | |||
− | '''ARMv7-M Memory Attributes''' |
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The Cortex-M memory attributes include the following bits: |
The Cortex-M memory attributes include the following bits: |
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+ | {| class="wikitable" |
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− | |||
+ | |- |
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− | ''Bufferable:'' |
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− | Write to memory can be carried out by a write buffer while the processor continues on next instruction execution. |
+ | | Bufferable || Write to memory can be carried out by a write buffer while the processor continues on next instruction execution. |
+ | |- |
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− | |||
+ | | Cacheable || Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution. |
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− | ''Cacheable:'' |
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+ | |- |
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− | Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution. |
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+ | | Sharable || Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region. |
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− | |||
+ | |- |
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− | ''Sharable:'' |
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+ | | TEX || Type Extension field |
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− | Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region. |
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+ | |} |
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− | |||
− | ''TEX:'' |
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− | Type Extension field |
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These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0): |
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0): |
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+ | 31:29 Reserved |
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− | <nowiki> |
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+ | 28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault) |
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− | 31:29 Reserved |
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+ | 27 Reserved |
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− | 28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault) |
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+ | 26:24 AP R/W — Data Access Permission field |
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− | 27 Reserved |
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+ | 23:22 Reserved |
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− | 26:24 AP R/W — Data Access Permission field |
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+ | 21:19 TEX R/W — Type Extension field |
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− | 23:22 Reserved |
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− | + | 18 S R/W — Shareable |
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− | + | 17 C R/W — Cacheable |
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− | + | 16 B R/W — Bufferable |
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− | + | 15:8 SRD R/W — Subregion disable |
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+ | 7:6 Reserved |
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− | 15:8 SRD R/W — Subregion disable |
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+ | 5:1 REGION SIZE R/W — MPU Protection Region size |
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− | 7:6 Reserved |
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− | + | 0 ENABLE R/W — Region enable |
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− | 0 ENABLE R/W — Region enable |
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− | </nowiki> |
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+ | Possible values are: |
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− | <nowiki> |
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− | TEX C B Description Region Shareability |
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− | b000 0 0 Strongly ordered (transfers carry out and complete in programmed order) Shareable |
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− | b000 0 1 Shared device (write can be buffered) Shareable |
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− | b000 1 0 Outer and inner write-through; no write allocate [S] |
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− | b000 1 1 Outer and inner write-back; no write allocate [S] |
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− | b001 0 0 Outer and inner non cacheable [S] |
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− | b001 0 1 Reserved Reserved |
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− | b001 1 0 Implementation defined – |
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− | b001 1 1 Outer and inner write-back; write and read allocate [S] |
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− | b010 0 0 Nonshared device Not shared |
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− | b010 0 1 Reserved Reserved |
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− | b010 1 X Reserved Reserved |
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− | b1BB A A Cached memory; BB = outer policy, AA = inner policy [S] |
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− | </nowiki> |
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+ | {| class="wikitable" |
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− | Encoding of Inner and Outer Cache Policy when Most Significant Bit of TEX Is Set to 1: |
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+ | |- |
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− | <nowiki> |
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+ | ! colspan="4" | Settings || rowspan="66" | || colspan="3" | Resulting attributes |
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− | Memory Attribute Encoding (AA and BB) Cache Policy |
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+ | |- |
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− | 00 Noncacheable |
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+ | ! TEX || C || B || S || Memory Type || Shareability || Other attributes |
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− | 01 Write back, write, and read allocate |
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+ | |- style="vertical-align:middle;" |
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− | 10 Write through, no write allocate |
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+ | | rowspan="8" | 000 |
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− | 11 Write back, no write allocate |
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+ | | rowspan="4" | 0 |
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− | </nowiki> |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | rowspan="2" | Strongly ordered |
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+ | | rowspan="4" | Shareable<ref name="SBit">The value of the S-bit is ignored in this encoding.</ref> |
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+ | | rowspan="4" | - |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | rowspan="2" | Device |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | rowspan="6" | Normal |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write through, no write allocate<br />Inner write through, no write allocate |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | | Shareable |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, no write allocate<br />Inner write back, no write allocate |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | | Shareable |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="8" | 001 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer noncacheable<br />Inner noncacheable |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | | Shareable |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | rowspan="2" colspan="3" style="text-align:center;" | Reserved encoding |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | rowspan="2" colspan="3" style="text-align:center;" | Implementation defined encoding |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | rowspan="2" | Normal |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, write and read allocate<br />Inner write back, write and read allocate |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | | Shareable |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="8" | 010 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | rowspan="2" | Device |
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+ | | rowspan="2" | Not shareable<ref name="SBit" /> |
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+ | | rowspan="2" | - |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | rowspan="14" colspan="3" style="text-align:center;" | Reserved encoding |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="8" | 011 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- style="vertical-align:middle;" |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | |- style="vertical-align:middle;" |
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+ | | 1 |
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+ | |- |
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+ | | rowspan="8" | 100 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | rowspan="32" | Normal |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer noncacheable<br />Inner noncacheable |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer noncacheable<br />Inner write back, write and read allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer noncacheable<br />Inner write through, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer noncacheable<br />Inner write back, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="8" | 101 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, write and read allocate<br />Inner noncacheable |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, write and read allocate<br />Inner write back, write and read allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, write and read allocate<br />Inner write through, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, write and read allocate<br />Inner write back, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="8" | 110 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write through, no write allocate<br />Inner noncacheable |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write through, no write allocate<br />Inner write back, write and read allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write through, no write allocate<br />Inner write through, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write through, no write allocate<br />Inner write back, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="8" | 111 |
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+ | | rowspan="4" | 0 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, no write allocate<br />Inner noncacheable |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, no write allocate<br />Inner write back, write and read allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="4" | 1 |
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+ | | rowspan="2" | 0 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, no write allocate<br />Inner write through, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |- |
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+ | | rowspan="2" | 1 |
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+ | | 0 |
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+ | | Not shareable |
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+ | | rowspan="2" | Outer write back, no write allocate<br />Inner write back, no write allocate |
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+ | |- |
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+ | | 1 |
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+ | | Shareable |
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+ | |} |
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+ | <references/> |
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With embOS-MPU Cortex-M the ''Attributes'' parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register. |
With embOS-MPU Cortex-M the ''Attributes'' parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register. |
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− | + | === Example === |
|
− | <nowiki> |
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Setting the memory attribute of a region to Write back, no write allocate: |
Setting the memory attribute of a region to Write back, no write allocate: |
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+ | <source lang="C"> |
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− | #define TEX_100 (4u << 19) |
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+ | #define TEX_100 (4u << 3) |
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#define CACHEABLE (1u << 1) |
#define CACHEABLE (1u << 1) |
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#define BUFFERABLE (1u << 0) |
#define BUFFERABLE (1u << 0) |
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OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE); |
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE); |
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+ | </source> |
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− | |||
− | </nowiki> |
Latest revision as of 10:27, 29 June 2021
With embOS-MPU different memory regions with separate access rights and memory attributes can be defined. A memory region can be added with OS_MPU_AddRegion().
OS_MPU_AddRegion()
OS_MPU_AddRegion() has the following prototype:
void OS_MPU_AddRegion(OS_TASK* pTask,
OS_U32 BaseAddr,
OS_U32 Size,
OS_U32 Permissions,
OS_U32 Attributes);
ARMv7-M Memory Attributes
embOS-MPU includes defines for the permissions (e.g. OS_MPU_READONLY), but not for the attributes since they are core specific.
The Cortex-M memory attributes include the following bits:
Bufferable | Write to memory can be carried out by a write buffer while the processor continues on next instruction execution. |
Cacheable | Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution. |
Sharable | Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region. |
TEX | Type Extension field |
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
31:29 Reserved 28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault) 27 Reserved 26:24 AP R/W — Data Access Permission field 23:22 Reserved 21:19 TEX R/W — Type Extension field 18 S R/W — Shareable 17 C R/W — Cacheable 16 B R/W — Bufferable 15:8 SRD R/W — Subregion disable 7:6 Reserved 5:1 REGION SIZE R/W — MPU Protection Region size 0 ENABLE R/W — Region enable
Possible values are:
Settings | Resulting attributes | ||||||
---|---|---|---|---|---|---|---|
TEX | C | B | S | Memory Type | Shareability | Other attributes | |
000 | 0 | 0 | 0 | Strongly ordered | Shareable[1] | - | |
1 | |||||||
1 | 0 | Device | |||||
1 | |||||||
1 | 0 | 0 | Normal | Not shareable | Outer write through, no write allocate Inner write through, no write allocate | ||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write back, no write allocate Inner write back, no write allocate | ||||
1 | Shareable | ||||||
001 | 0 | 0 | 0 | Not shareable | Outer noncacheable Inner noncacheable | ||
1 | Shareable | ||||||
1 | 0 | Reserved encoding | |||||
1 | |||||||
1 | 0 | 0 | Implementation defined encoding | ||||
1 | |||||||
1 | 0 | Normal | Not shareable | Outer write back, write and read allocate Inner write back, write and read allocate | |||
1 | Shareable | ||||||
010 | 0 | 0 | 0 | Device | Not shareable[1] | - | |
1 | |||||||
1 | 0 | Reserved encoding | |||||
1 | |||||||
1 | 0 | 0 | |||||
1 | |||||||
1 | 0 | ||||||
1 | |||||||
011 | 0 | 0 | 0 | ||||
1 | |||||||
1 | 0 | ||||||
1 | |||||||
1 | 0 | 0 | |||||
1 | |||||||
1 | 0 | ||||||
1 | |||||||
100 | 0 | 0 | 0 | Normal | Not shareable | Outer noncacheable Inner noncacheable | |
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer noncacheable Inner write back, write and read allocate | ||||
1 | Shareable | ||||||
1 | 0 | 0 | Not shareable | Outer noncacheable Inner write through, no write allocate | |||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer noncacheable Inner write back, no write allocate | ||||
1 | Shareable | ||||||
101 | 0 | 0 | 0 | Not shareable | Outer write back, write and read allocate Inner noncacheable | ||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write back, write and read allocate Inner write back, write and read allocate | ||||
1 | Shareable | ||||||
1 | 0 | 0 | Not shareable | Outer write back, write and read allocate Inner write through, no write allocate | |||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write back, write and read allocate Inner write back, no write allocate | ||||
1 | Shareable | ||||||
110 | 0 | 0 | 0 | Not shareable | Outer write through, no write allocate Inner noncacheable | ||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write through, no write allocate Inner write back, write and read allocate | ||||
1 | Shareable | ||||||
1 | 0 | 0 | Not shareable | Outer write through, no write allocate Inner write through, no write allocate | |||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write through, no write allocate Inner write back, no write allocate | ||||
1 | Shareable | ||||||
111 | 0 | 0 | 0 | Not shareable | Outer write back, no write allocate Inner noncacheable | ||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write back, no write allocate Inner write back, write and read allocate | ||||
1 | Shareable | ||||||
1 | 0 | 0 | Not shareable | Outer write back, no write allocate Inner write through, no write allocate | |||
1 | Shareable | ||||||
1 | 0 | Not shareable | Outer write back, no write allocate Inner write back, no write allocate | ||||
1 | Shareable |
With embOS-MPU Cortex-M the Attributes parameter is shifted by 16 bits and set in the Cortex-M Region Base Attribute and Size Register.
Example
Setting the memory attribute of a region to Write back, no write allocate:
#define TEX_100 (4u << 3)
#define CACHEABLE (1u << 1)
#define BUFFERABLE (1u << 0)
OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, TEX_100 | BUFFERABLE | CACHEABLE);