Difference between revisions of "J-Link LITE ARM V8"
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This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Link LITE ARM V8'''. |
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Link LITE ARM V8'''. |
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+ | {{DisclaimerLegacyJLink|J-Link LITE ARM V8}} |
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− | {{Note|The J-Link LITE ARM V8 has been superseded and as such is considered a legacy device. |
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− | This device is not eligible for support by SEGGER. |
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− | Refer to the [[J-Link Model Overview]] for a list of most recent devices by SEGGER.}} |
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Latest revision as of 12:04, 11 January 2022
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link LITE ARM V8.
Note:
The J-Link LITE ARM V8 has been superseded and as such is considered a legacy device.
This device is not eligible for support by SEGGER.
Refer to the J-Link Model Overview for a list of most recent devices by SEGGER.
We recommend to make use of the SEGGER Trade-In-Program to upgrade to the current version of the product.
When new features are added, articles for legacy models may not be updated.
Contents
Hardware and Software Features
Hardware version | 8 | |||||
---|---|---|---|---|---|---|
Hardware Features | ||||||
USB 2.0 Full Speed | ![]() | |||||
JTAG interface | ![]() | |||||
SWD interface | ![]() | |||||
SWO interface | ![]() | |||||
SPI interface | ![]() | |||||
QSPI interface | ![]() | |||||
Microchip ICSP interface | ![]() | |||||
Renesas FINE interface | ![]() | |||||
SiLabs C2 2-wire interface | ![]() | |||||
ETB Trace ARM7/9 | ![]() | |||||
ETB Trace Cortex-M | ![]() | |||||
ETB Trace Cortex-A/R | ![]() | |||||
ETM Trace Cortex-M | ![]() | |||||
VCOM | ![]() | |||||
Memory Stop mode support | ![]() | |||||
Cortex-M Monitor Mode debugging | ![]() | |||||
SWD Multi-Drop | ![]() | |||||
CMSIS-DAP mode | ![]() | |||||
ARM legacy Cores | ||||||
ARM7 | ![]() | |||||
ARM9 | ![]() | |||||
ARM11 | ![]() | |||||
ARM Cortex Cores | ||||||
Cortex-A5 | ![]() | |||||
Cortex-A7 | ![]() | |||||
Cortex-A8 | ![]() | |||||
Cortex-A9 | ![]() | |||||
Cortex-A12 | ![]() | |||||
Cortex-A15 | ![]() | |||||
Cortex-A17 | ![]() | |||||
Cortex-A53 | ![]() | |||||
Cortex-A57 | ![]() | |||||
Cortex-A72 | ![]() | |||||
Cortex-M0 | ![]() | |||||
Cortex-M0+ | ![]() | |||||
Cortex-M1 | ![]() | |||||
Cortex-M3 | ![]() | |||||
Cortex-M4 | ![]() | |||||
Cortex-M7 | ![]() | |||||
Cortex-M23 | ![]() | |||||
Cortex-M33 | ![]() | |||||
Cortex-R4 | ![]() | |||||
Cortex-R5 | ![]() | |||||
Cortex-R8 | ![]() | |||||
SC000 (M0 secure) | ![]() | |||||
SC300 (M3 secure) | ![]() | |||||
RISC-V | ||||||
RV32 | ![]() | |||||
RV64 | ![]() | |||||
Microchip PIC32 | ||||||
PIC32MX | ![]() | |||||
PIC32MZ | ![]() | |||||
SiLabs 8051 | ||||||
EFM8 | ![]() | |||||
Renesas RX | ||||||
RX110 | ![]() | |||||
RX111 | ![]() | |||||
RX210 | ![]() | |||||
RX21A | ![]() | |||||
RX220 | ![]() | |||||
RX610 | ![]() | |||||
RX621 | ![]() | |||||
RX62G | ![]() | |||||
RX62G | ![]() | |||||
RX62N | ![]() | |||||
RX62T | ![]() | |||||
RX630 | ![]() | |||||
RX631 | ![]() | |||||
RX63N | ![]() | |||||
RX63T | ![]() | |||||
RX64M | ![]() |