Difference between revisions of "ST STM32WL"
Line 1: | Line 1: | ||
__TOC__ |
__TOC__ |
||
− | The STM32WL5/WLE devices are |
+ | The ST STM32WL5/WLE devices are ultra-low-power long-range wireless MCUs. |
+ | * The STM32WL5 are dual core devices with a Cortex-M4 as main core and an additional Cortex-M0. |
||
+ | * The STM32WLE are single core Cortex-M4 devices. |
||
+ | |||
+ | A list of ST STM32WL devices supported by J-Link can be found on the [https://www.segger.com/supported-devices/search/STM32WL SEGGER homepage]. |
||
+ | |||
==Internal Flash== |
==Internal Flash== |
||
===Supported Regions=== |
===Supported Regions=== |
||
Line 9: | Line 14: | ||
*Option Bytes (0x1FFF7800 - 0x1FFF7FFF) |
*Option Bytes (0x1FFF7800 - 0x1FFF7FFF) |
||
For now, the J-Link supports the main memory, only. |
For now, the J-Link supports the main memory, only. |
||
+ | |||
==Evaluation Boards== |
==Evaluation Boards== |
||
*ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2 |
*ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2 |
Revision as of 16:19, 18 November 2022
The ST STM32WL5/WLE devices are ultra-low-power long-range wireless MCUs.
- The STM32WL5 are dual core devices with a Cortex-M4 as main core and an additional Cortex-M0.
- The STM32WLE are single core Cortex-M4 devices.
A list of ST STM32WL devices supported by J-Link can be found on the SEGGER homepage.
Internal Flash
Supported Regions
The internal flash is divided into 3 different regions:
- Main memory (0x08000000 - 0x0803FFFF)
- System memory (0x1FFF0000 - 0x1FFF6FFF)
- OTP area (0x1FFF7000 - 0x1FFF73FF)
- Option Bytes (0x1FFF7800 - 0x1FFF7FFF)
For now, the J-Link supports the main memory, only.
Evaluation Boards
- ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2
Example Application
- ST STM32WL55JC2 evaluation board: File:ST STM32WL55JC2 TestProject ES V510b.zip