Difference between revisions of "TI CC1311P3"
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| − | The '''TI CC131P3''' are SimpleLink™ High-Performance Sub-1 GHz Wireless |
+ | The '''TI CC131P3''' are SimpleLink™ High-Performance Sub-1 GHz Wireless MCUs with Cortex-M4 Core. |
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==Watchdog Handling== |
==Watchdog Handling== |
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| − | *The device |
+ | *The device has a watchdog WDT, which is disabled by default. |
| + | *The watchdog is not handled during flash programming. |
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| − | *The device has a watchdog [WATCHDOGNAME]. |
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| − | *The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| − | |||
| − | |||
| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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===Reset=== |
===Reset=== |
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| + | *The device uses custom reset, after Boot ROM execution target is halted. |
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| − | *The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The device uses custom reset:..... |
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==Limitations== |
==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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| − | Attach is |
+ | Attach is supported. |
===Security=== |
===Security=== |
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| + | If device is secured, device can be unsecured by mass erase if user confirms. |
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| + | |||
==Evaluation Boards== |
==Evaluation Boards== |
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| − | * |
+ | *TI [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard |
==Example Application== |
==Example Application== |
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Revision as of 11:00, 13 June 2023
The TI CC131P3 are SimpleLink™ High-Performance Sub-1 GHz Wireless MCUs with Cortex-M4 Core.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x00000000 | 356 KB | 
|
Watchdog Handling
- The device has a watchdog WDT, which is disabled by default.
- The watchdog is not handled during flash programming.
Device Specific Handling
Connect
Reset
- The device uses custom reset, after Boot ROM execution target is halted.
Limitations
Attach
Attach is supported.
Security
If device is secured, device can be unsecured by mass erase if user confirms.
Evaluation Boards
- TI [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
