Difference between revisions of "ST STM32G4"
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This article describes device specifics of the ST STM32G4 series devices. |
This article describes device specifics of the ST STM32G4 series devices. |
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The STM32G4 devices are Cortex-M4 based MCUs with low-power functionality. |
The STM32G4 devices are Cortex-M4 based MCUs with low-power functionality. |
Latest revision as of 11:21, 15 May 2024
This article describes device specifics of the ST STM32G4 series devices. The STM32G4 devices are Cortex-M4 based MCUs with low-power functionality.
Contents
Flash
The following flash regions are supported by J-Link.
Device | Range | Total size |
---|---|---|
Main flash memory | ||
STM32G4xxx6 | 0x0800_0000 - 0x0800_7FFF | 32 KB |
STM32G4xxx8 | 0x0800_0000 - 0x0800_FFFF | 64 KB |
STM32G4xxxB | 0x0800_0000 - 0x0801_FFFF | 128 KB |
STM32G4xxxC | 0x0800_0000 - 0x0803_FFFF | 256 KB |
STM32G4xxxE | 0x0800_0000 - 0x0807_FFFF | 512 KB |
Option bytes[1] | ||
All | 0x1FFF_7800 - 0x1FFF_782F | 48 bytes |
STM32G4xxxB/C/E | 0x1FFF_F800 - 0x1FFF_F82F | 48 bytes |
- ↑ See: Option byte programming
Reset
For the STM32G4 devices, the Cortex-M default reset strategy is used.
Debug specific
Please refer to the generic STM32 article.
Option byte programming
Please refer to the generic STM32 article.
Securing/unsecuring the device
Please refer to the generic STM32 article.
STM32G47xx Flash Dual Bank Mode
The ST STM32G47xx series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte nDBANK. By default, the value of this option byte is DBANK == 1, which means that the flash is configured as dual bank memory while DBANK == 0 means that the flash is configured as single bank memory flash. The total flash size is exactly the same for both modes.
Problem description
- The sector layout is different depending on the DBANK bit
- The flash algorithm has to behave different (pass different sector indices to erase sector)
By default, the J-Link flash loader assumes that the flash controller is configured for the dual bank flash layout (DBANK == 1) because it is the default configuration. In case of the flash controller is configured for the single bank flash layout (DBANK == 0), the default flash algorithm / sector layout won't work.
Solution
J-Link offers two different loaders for those devices. Depending on DBANK settings, either "SingleBank" or "DualBank" loader must be used. For more information on multiple loaders and how to use them, please see the article on it.
Tracing on STM32G4 series
This section describes how to get started with trace on the ST STM32G4 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
- The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
- To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Tracing on ST STM32G484
Minimum requirements
In order to use trace on the ST STM32G484 MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.80a or later
- Ozone V3.20 or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project has been tested with the minimum requirements mentioned above and a STM32G474-EVAL board.
Example project: ST_STM32G484_TracePins.zip
Specifics/Limitations
The eval board used for this example setup needs some hardware modifications for trace to work reliably as the trace pins are shared with multiple peripherals that would otherwise impact the signal quality. For more information consult the boards user manual. Please note that these modifications will also disable the JTAG interface so only SWD can be used on this particular board in parallel with pin tracing.
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.