Difference between revisions of "Infineon CCG7S"
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| Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
| Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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==Watchdog Handling== |
==Watchdog Handling== |
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*The device does not have a watchdog. |
*The device does not have a watchdog. |
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− | ==Multi-Core Support [OPTIONAL]== |
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− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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− | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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− | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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− | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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− | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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− | ===Main core=== |
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− | ====Init/Setup==== |
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− | *Initializes the ECC RAM, see [[XXX | XXX]] |
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− | *Enables debugging |
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− | ====Reset==== |
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− | *Device specific reset is performed, see [[XXX | XXX]] |
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− | ====Attach==== |
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− | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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− | ===Secondary core(s)=== |
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− | ====Init/Setup==== |
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− | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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− | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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− | ====Reset==== |
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− | No reset is performed. |
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− | ====Attach==== |
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− | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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+ | *The device has a special reset sequence. |
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+ | |||
===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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− | *The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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− | *The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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− | *The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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− | *The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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− | *The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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− | *The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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− | *The device uses custom reset:..... |
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− | ==Limitations== |
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− | ===Dual Core Support=== |
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− | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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− | ===Attach=== |
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− | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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− | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
Revision as of 12:33, 27 December 2023
The Infineon CCG7S are Automotive USB single-port USB-C Power Delivery with buck-boost controller based on Cortex-M0.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00000000 | 128 KB |
Watchdog Handling
- The device does not have a watchdog.
Device Specific Handling
Connect
- The device has a special reset sequence.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.