Difference between revisions of "GigaDevice GD32F5"

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(Internal Flash)
Line 11: Line 11:
 
| Main flash || 0x08000000 || Up to 3072 KB || style="text-align:center;"| {{YES}}
 
| Main flash || 0x08000000 || Up to 3072 KB || style="text-align:center;"| {{YES}}
 
|-
 
|-
| OTP Block || 0x1FFF0000 || 528 B || style="text-align:center;"| {{NO}}
+
| OTP Block 1 (data) || 0x1FF00000 || 8 KB || style="text-align:center;"| {{NO}}
 
|-
 
|-
| Option Bytes 0 (GD32F403 only) || 0x1FFFE000 || 16 B || style="text-align:center;"| {{YES}}
+
| OTP Block 2 (data) || 0x1FF20000 || 512 B || style="text-align:center;"| {{NO}}
 
|-
 
|-
| Option Bytes Bank 0<br>(GD32F4xx except GD32F403) || 0x1FFFC000 || 16 B || style="text-align:center;"| {{NO}}
+
| OTP Block 1 (lock) || 0x1FF20200 || 16 B || style="text-align:center;"| {{NO}}
 
|-
 
|-
| Option Bytes Bank 1 || 0x1FFEC000 || 16 B || style="text-align:center;"| {{NO}}
+
| OTP Block 2 (lock) || 0x1FF20210 || 16 B || style="text-align:center;"| {{NO}}
  +
|-
 
  +
| OTP0 Block (data) || 0x1FFF7800 || 64 B || style="text-align:center;"| {{NO}}
  +
|-
  +
| OTP0 Block (lock) || 0x1FFF7840 || 16 B || style="text-align:center;"| {{NO}}
  +
|-
  +
| Option Bytes (Bank 0) || 0x1FFFC000 || 16 B || style="text-align:center;"| {{NO}}
  +
|-
  +
| Option Bytes (Bank 1) || 0x1FFEC000 || 16 B || style="text-align:center;"| {{NO}}
 
|}
 
|}
   

Revision as of 09:03, 25 June 2024

The GigaDevice GD32F5 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M33 processor.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Main flash 0x08000000 Up to 3072 KB YES.png
OTP Block 1 (data) 0x1FF00000 8 KB NO.png
OTP Block 2 (data) 0x1FF20000 512 B NO.png
OTP Block 1 (lock) 0x1FF20200 16 B NO.png
OTP Block 2 (lock) 0x1FF20210 16 B NO.png
OTP0 Block (data) 0x1FFF7800 64 B NO.png
OTP0 Block (lock) 0x1FFF7840 16 B NO.png
Option Bytes (Bank 0) 0x1FFFC000 16 B NO.png
Option Bytes (Bank 1) 0x1FFEC000 16 B NO.png

Watchdog Handling

  • The device does have 2 watchdogs, FWDGT and WWDGT.
  • The WWDGT watchdog is fed during flash programming.

Device Specific Handling

Connect

  • On Connect, protection level is checked. For further information regarding this, please click here.

Currently only GD32F403 is supported.

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

Example Application