Difference between revisions of "J-Trace PRO Cortex-M V1"
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|colspan="7"| Hardware Features |
|colspan="7"| Hardware Features |
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− | ! style="text-align:left;"|USB 2.0 Hi-Speed |
+ | ! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|USB 3.0 SuperSpeed |
+ | ! style="text-align:left;"|USB 3.0 SuperSpeed || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|Gigabit-Ethernet |
+ | ! style="text-align:left;"|Gigabit-Ethernet || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|cJTAG interface |
+ | ! style="text-align:left;"|cJTAG interface || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|JTAG interface |
+ | ! style="text-align:left;"|JTAG interface || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|SWD interface |
+ | ! style="text-align:left;"|SWD interface || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|SWO interface |
+ | ! style="text-align:left;"|SWO interface || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|ETB Trace Cortex-M |
+ | ! style="text-align:left;"|ETB Trace Cortex-M || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|ETM Trace Cortex-M |
+ | ! style="text-align:left;"|ETM Trace Cortex-M || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Streaming Trace |
+ | ! style="text-align:left;"|Streaming Trace || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|VCOM |
+ | ! style="text-align:left;"|VCOM || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|Memory Stop mode support |
+ | ! style="text-align:left;"|Memory Stop mode support || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M Monitor Mode debugging |
+ | ! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|5 V Target Supply |
+ | ! style="text-align:left;"|5 V Target Supply || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|SWD Multi-Drop |
+ | ! style="text-align:left;"|SWD Multi-Drop || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|CMSIS-DAP mode |
+ | ! style="text-align:left;"|CMSIS-DAP mode || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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|- style="text-align:center" |
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|colspan="7"| ARM Cortex Cores |
|colspan="7"| ARM Cortex Cores |
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− | ! style="text-align:left;"|Cortex-A53 |
+ | ! style="text-align:left;"|Cortex-A53 || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-A57 |
+ | ! style="text-align:left;"|Cortex-A57 || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-A72 |
+ | ! style="text-align:left;"|Cortex-A72 || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M0 |
+ | ! style="text-align:left;"|Cortex-M0 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M0+ |
+ | ! style="text-align:left;"|Cortex-M0+ || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M1 |
+ | ! style="text-align:left;"|Cortex-M1 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M3 |
+ | ! style="text-align:left;"|Cortex-M3 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M4 |
+ | ! style="text-align:left;"|Cortex-M4 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M7 |
+ | ! style="text-align:left;"|Cortex-M7 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M23 |
+ | ! style="text-align:left;"|Cortex-M23 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|Cortex-M33 |
+ | ! style="text-align:left;"|Cortex-M33 || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|SC000 (M0 secure) |
+ | ! style="text-align:left;"|SC000 (M0 secure) || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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− | ! style="text-align:left;"|SC300 (M3 secure) |
+ | ! style="text-align:left;"|SC300 (M3 secure) || {{YES}} |
− | | [[File:YES.png|20px|link=]] |
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|- style="text-align:center" |
|- style="text-align:center" |
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|colspan="7"| RISC-V |
|colspan="7"| RISC-V |
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− | ! style="text-align:left;"|RV32 |
+ | ! style="text-align:left;"|RV32 || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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− | ! style="text-align:left;"|RV64 |
+ | ! style="text-align:left;"|RV64 || {{NO}} |
− | | [[File:NO.png|20px|link=]] |
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Revision as of 15:22, 10 December 2021
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Trace PRO Cortex-M V1.
Note:
The J-Trace PRO Cortex-M V1 has been superseded and as such is considered a legacy device. This device is not eligible for support by SEGGER.
Refer to the J-Link Model Overview for a list of most recent devices by SEGGER.
Contents
Hardware and Software Features
Hardware version | 1 | |||||
---|---|---|---|---|---|---|
Hardware Features | ||||||
USB 2.0 Hi-Speed | ||||||
USB 3.0 SuperSpeed | ||||||
Gigabit-Ethernet | ||||||
cJTAG interface | ||||||
JTAG interface | ||||||
SWD interface | ||||||
SWO interface | ||||||
ETB Trace Cortex-M | ||||||
ETM Trace Cortex-M | ||||||
Streaming Trace | ||||||
VCOM | ||||||
Memory Stop mode support | ||||||
Cortex-M Monitor Mode debugging | ||||||
5 V Target Supply | ||||||
SWD Multi-Drop | ||||||
CMSIS-DAP mode | ||||||
ARM Cortex Cores | ||||||
Cortex-A53 | ||||||
Cortex-A57 | ||||||
Cortex-A72 | ||||||
Cortex-M0 | ||||||
Cortex-M0+ | ||||||
Cortex-M1 | ||||||
Cortex-M3 | ||||||
Cortex-M4 | ||||||
Cortex-M7 | ||||||
Cortex-M23 | ||||||
Cortex-M33 | ||||||
SC000 (M0 secure) | ||||||
SC300 (M3 secure) | ||||||
RISC-V | ||||||
RV32 | ||||||
RV64 |