Difference between revisions of "PSoC 4xxx series"
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− | This page contains information about the |
+ | This page contains information about the Infineon PSoC 4xxx series. |
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__TOC__ |
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=Connection behavior= |
=Connection behavior= |
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=Readout protection= |
=Readout protection= |
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− | The following section explains how to set |
+ | The following section explains how to set Infineon PSoC 4 devices in protected state and how to unprotect them. |
== Securing device after programming == |
== Securing device after programming == |
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− | The |
+ | The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to secure the device consists of multiple read / write accesses to special function registers of the CY8C4xxx and CYBLExxxx series devices. |
=== Via J-Flash / Flasher ARM === |
=== Via J-Flash / Flasher ARM === |
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− | The sequence to secure the device, needs to be added to the exit-steps of the J-Flash project. The exit steps will be executed at the end of an successful auto-programming process (''Target -> Auto''). J-Flash comes with an example project for the |
+ | The sequence to secure the device, needs to be added to the exit-steps of the J-Flash project. The exit steps will be executed at the end of an successful auto-programming process (''Target -> Auto''). J-Flash comes with an example project for the Infineon CYBLE-214009-00 device which contains a secure device programming sequence ([[File:Cypress_CYBLE_214009-00.jflash]]). This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure and can be adapted to fit custom requirements, by re-selecting the required device within the J-Flash project. |
[[File:Wiki-Cypress_CY8C4xxx_CYBLExxxx_ProtectCPU.png]] |
[[File:Wiki-Cypress_CY8C4xxx_CYBLExxxx_ProtectCPU.png]] |
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− | '''Note:''' PSoC4100/4200 target devices use different addresses for the SYSREQ and SYSARG registers. They are located at 0x40000004 and 0x40000008 instead. For more information please consult the |
+ | '''Note:''' PSoC4100/4200 target devices use different addresses for the SYSREQ and SYSARG registers. They are located at 0x40000004 and 0x40000008 instead. For more information please consult the Infineon Programming Specifications user guide. |
'''Note2:''' The clock of some PSoC4 target devices must be set to 48MHz before calling the locking/unlocking sequence. This can be achieved by using the "Configure Clock" Command. |
'''Note2:''' The clock of some PSoC4 target devices must be set to 48MHz before calling the locking/unlocking sequence. This can be achieved by using the "Configure Clock" Command. |
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[[File:Wiki-Cypress_PSoC-BL_ProtectCPU.png]] |
[[File:Wiki-Cypress_PSoC-BL_ProtectCPU.png]] |
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=== Protection levels === |
=== Protection levels === |
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− | For |
+ | For Infineon PSoC4 devices three levels of protection can be set by altering the ''SYSARG chip protection'' step in the examples above: |
{| class="wikitable" |
{| class="wikitable" |
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== Unsecuring device before reprogramming == |
== Unsecuring device before reprogramming == |
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− | The |
+ | The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to unsecure the device consists of multiple read / write accesses to special function registers of the Infineon CY8C4xxx and CYBLExxxx series devices MCU. |
=== Via J-Flash / Flasher ARM === |
=== Via J-Flash / Flasher ARM === |
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− | J-Flash('''v6.31k and following''') detects if the device is secured. In case of a secured device it will unsecure it. This sequence applies for all |
+ | J-Flash('''v6.31k and following''') detects if the device is secured. In case of a secured device it will unsecure it. This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure. |
Revision as of 18:27, 10 February 2022
This page contains information about the Infineon PSoC 4xxx series.
Contents
Connection behavior
The connect sequence of PSoC 4 devices is very time critical and is performed from the J-Link's side directly.
A locked PSoC 4 device is automatically set to open if it was in protected state. If the device was unlocked, the internal memory is again in erased state.
Readout protection
The following section explains how to set Infineon PSoC 4 devices in protected state and how to unprotect them.
Securing device after programming
The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to secure the device consists of multiple read / write accesses to special function registers of the CY8C4xxx and CYBLExxxx series devices.
Via J-Flash / Flasher ARM
The sequence to secure the device, needs to be added to the exit-steps of the J-Flash project. The exit steps will be executed at the end of an successful auto-programming process (Target -> Auto). J-Flash comes with an example project for the Infineon CYBLE-214009-00 device which contains a secure device programming sequence (File:Cypress CYBLE 214009-00.jflash). This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure and can be adapted to fit custom requirements, by re-selecting the required device within the J-Flash project.
Note: PSoC4100/4200 target devices use different addresses for the SYSREQ and SYSARG registers. They are located at 0x40000004 and 0x40000008 instead. For more information please consult the Infineon Programming Specifications user guide.
Note2: The clock of some PSoC4 target devices must be set to 48MHz before calling the locking/unlocking sequence. This can be achieved by using the "Configure Clock" Command.
Protection levels
For Infineon PSoC4 devices three levels of protection can be set by altering the SYSARG chip protection step in the examples above:
Value | Effect |
0x0001E0B6 | Read protection level open. Device is unprotected |
0x0002E0B6 | Read protection level protected. Device is protected. Setting the mode to open again causes a mass erase. |
0x0004E0B6 | Read protection level kill. Device is protected. The protection level cannot be changed anymore. Setting to kill mode is permanent and makes the device unrecoverable. |
Unsecuring device before reprogramming
The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to unsecure the device consists of multiple read / write accesses to special function registers of the Infineon CY8C4xxx and CYBLExxxx series devices MCU.
Via J-Flash / Flasher ARM
J-Flash(v6.31k and following) detects if the device is secured. In case of a secured device it will unsecure it. This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure.