Difference between revisions of "Codasip L50"
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The Codasip L50 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: |
The Codasip L50 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: |
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* L50 (no FPU) |
* L50 (no FPU) |
Latest revision as of 11:08, 16 May 2024
The Codasip L50 is a 32-bit (RV32) core, designed by Codasip. It is available in 2 variants:
- L50 (no FPU)
- L50F (incl. FPU)
Minimum required J-Link software version
The L50 / L50F device selection is supported since V7.24 of the J-Link software.
RTT support
- RTT is automatically supported by J-Link if the core supports system bus access (SBA)
- As SBA is a configuration option of the core, the configuration option must be chosen to have RTT support
HSS support
See RTT.