Infineon PMG1
Revision as of 10:49, 13 May 2024 by Torben.scharping (talk | contribs)
The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00000000 | Up to 256 KB |
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
- The device uses Cortex-M Core reset, no special handling necessary, like described here.
- The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses Cortex-A reset, no special handling necessary, like described here.
- The device uses Cortex-R reset, no special handling necessary, like described here.
- The device uses ARMv8-A reset, no special handling necessary, like described here.
- The device uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
Evaluation Boards
Example Application
Tracing
The following trace example projects are available:
- [Link to Board Article1]
- [Link to Board Article2]
- ...