J-Link PLUS V10
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link PLUS V10.
Note:
The J-Link PLUS V10 has been superseded and as such is considered a legacy device.
This device is not eligible for support by SEGGER.
Hardware and Software Features
Hardware Features | |||||||
USB 2.0 Full Speed | |||||||
---|---|---|---|---|---|---|---|
USB 2.0 Hi-Speed | |||||||
JTAG interface | |||||||
cJTAG interface | |||||||
SWD interface | |||||||
SWO interface | |||||||
SPI interface | |||||||
QSPI interface | |||||||
Microchip ICSP interface | |||||||
Renesas FINE interface | |||||||
SiLabs C2 2-wire interface | |||||||
ETB Trace ARM7/9 | |||||||
ETB Trace Cortex-M | |||||||
ETB Trace Cortex-A/R | |||||||
ETM Trace Cortex-M | |||||||
VCOM | |||||||
Memory Stop mode support | |||||||
Cortex-M Monitor Mode debugging | |||||||
SWD Multi-Drop | |||||||
ARM legacy Cores | |||||||
ARM7 | |||||||
ARM9 | |||||||
ARM11 | |||||||
ARM Cortex Cores | |||||||
Cortex-A5 | |||||||
Cortex-A7 | |||||||
Cortex-A8 | |||||||
Cortex-A9 | |||||||
Cortex-A12 | |||||||
Cortex-A15 | |||||||
Cortex-A17 | |||||||
Cortex-A53 | |||||||
Cortex-A57 | |||||||
Cortex-A72 | |||||||
Cortex-M0 | |||||||
Cortex-M0+ | |||||||
Cortex-M1 | |||||||
Cortex-M3 | |||||||
Cortex-M4 | |||||||
Cortex-M7 | |||||||
Cortex-M23 | |||||||
Cortex-M33 | |||||||
Cortex-R4 | |||||||
Cortex-R5 | |||||||
Cortex-R8 | |||||||
SC000 (M0 secure) | |||||||
SC300 (M3 secure) | |||||||
RISC-V | |||||||
RV32 | |||||||
RV64 | |||||||
Microchip PIC32 | |||||||
PIC32MX | |||||||
PIC32MZ | |||||||
SiLabs 8051 | |||||||
EFM8 | |||||||
Renesas RX | |||||||
RX110 | |||||||
RX111 | |||||||
RX210 | |||||||
RX21A | |||||||
RX220 | |||||||
RX610 | |||||||
RX621 | |||||||
RX62G | |||||||
RX62G | |||||||
RX62N | |||||||
RX62T | |||||||
RX630 | |||||||
RX631 | |||||||
RX63N | |||||||
RX63T | |||||||
RX64M |
Specifications
Specification | Value |
---|---|
General | |
Supported OS | Microsoft Windows (x86/x64), Linux (x86/x64/Arm), macOS (x86) |
Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
Operating temperature | +5°C ... +60°C |
Storage temperature | -20°C ... +65 °C |
Relative humidity (non-condensing) | Max. 90% rH |
Mechanical | |
Size (without cables) | 100mm x 53mm x 27mm |
Weight (without cables) | 70g |
Available interfaces | |
USB interface | USB 2.0 (Hi-Speed); USB Type B |
Target interface | JTAG 20-pin (14-pin and other adapters available) |
JTAG/SWD Interface, Electrical | |
Power supply | USB powered Max. 50mA + Target Supply current. |
Target interface voltage (VIF) | 1.2V ... 5V |
Target supply voltage | 5V (derived from USB voltage) |
Target supply current | Max. 300mA |
Reset Type | Open drain. Can be pulled low or tristated. |
Reset low level output voltage (VOL) | VOL <= 10% of VIF |
For the whole target voltage range (1.2V <= VIF <= 5V) | |
LOW level input voltage (VIL) | VIL <= 40% of VIF |
HIGH level input voltage (VIH) | VIH >= 60% of VIF |
For 1.2V <= VIF <= 3.6V | |
LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
For 3.6 <= VIF <= 5V | |
LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
JTAG/SWD Interface, Timing | |
Target interface speed | Max. 15 MHz |
SWO sampling frequency | Max. 30 MHz |
Data input rise time (Trdi) | Trdi <= 20ns |
Data input fall time (Tfdi) | Tfdi <= 20ns |
Data output rise time (Trdo) | Trdo <= 10ns |
Data output fall time (Tfdo) | Tfdo <= 10ns |
Clock rise time (Trc) | Trc <= 3ns |
Clock fall time (Tfc) | Tfc <= 3ns |