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Read / Write Protection

Security Bit

Excerpt from the Atmel SAMV71 reference Manual:

The SAM V71 features a security bit based on the GPNVM bit 0. When security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP, the ETM interface or the Fast Flash Programming Interface, is blocked. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.

Once the security bit is set, it will become effective immediately. The security bit can only be disabled from inside the application or via the ERASE-Pin. In order to set the security bit with J-Flash, the "Exit steps" can be used. An example J-Flash project that sets Bit 0 of GPNVM (= security bit) on a SAMV71Q21 target device can be found here:

Sector Write Protection

At the start of a download to flash, J-Link automatically detects and removes any sector write protection before proceeding the flash programming.