Difference between revisions of "ArteryTek AT-START-A403A"
(→Preparing for J-Link) |
|||
Line 26: | Line 26: | ||
*Power the board via CN4. |
*Power the board via CN4. |
||
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
||
− | [[File:Artery_AT-START- |
+ | [[File:Artery_AT-START-A403A_AT32A403AVGT7_connect.png|400px]] |
== Example Project== |
== Example Project== |
Revision as of 11:21, 8 February 2024
This article describes specifics for the Artery AT-START-FA403A evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 23 | VDD |
GND | J1 | 22 | GND |
TDI | J1 | 25 | PA15 |
TMS/SWDIO | J1 | 20 | PA13 |
TCK/SWCLK | J1 | 24 | PA14 |
TDO/SWO | J1 | 37 | PB3 |
RESET | J2 | 14 | NRST |
- Power the board via CN4.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-FA403A.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94j
- Embedded Studio: V7.20
- Hardware: Artery AT-START-FA403A
- Link: File:Artery AT-START-FA403A AT32FA403AVGT7 TestProject ES 7V20.zip