Difference between revisions of "ArteryTek AT-START-F402"
(→Preparing for J-Link) |
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| TDO/SWO || J1 || 23 || PB3 |
| TDO/SWO || J1 || 23 || PB3 |
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− | | RESET || J2 || |
+ | | RESET || J2 || 9 || NRST |
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− | *Power the board via USB |
+ | *Power the board via USB CN3. |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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[[File:Artery_AT-START-F402_AT32F402RCT7-7_connect.png|400px]] |
[[File:Artery_AT-START-F402_AT32F402RCT7-7_connect.png|400px]] |
Revision as of 14:16, 25 January 2024
This article describes specifics for the Artery AT-START-F402 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 32 | VDD |
GND | J1 | 31 | GND |
TDI | J1 | 18 | PA15 |
TMS/SWDIO | J1 | 14 | PA13/SWDIO |
TCK/SWCLK | J1 | 17 | PA14/SWCLK |
TDO/SWO | J1 | 23 | PB3 |
RESET | J2 | 9 | NRST |
- Power the board via USB CN3.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F402.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94h
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F402
- Link: File:Artery AT-START-F402 AT32F402RCT7-7 TestProject ES 7V20.zip