Difference between revisions of "ArteryTek AT-START-F403A"

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(Created page with "__TOC__ This article describes specifics for the Artery AT-START-F403 evaluation board.<br> 450px == Preparing for J-Li...")
 
m (Torben.scharping moved page Artery AT-START-F403A to ArteryTek AT-START-F403A)
 
(5 intermediate revisions by the same user not shown)
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__TOC__
  
__TOC__
   
−
This article describes specifics for the Artery AT-START-F403 evaluation board.<br>
 +
This article describes specifics for the ArteryTek AT-START-F403A evaluation board.<br>
−
[[File:Artery_AT-START-F403_AT32F403AVGT7_board.jpg|450px]]
 +
[[File:Artery_AT-START-F403A_AT32F403AVGT7_board.jpg|450px]]
   
 
== Preparing for J-Link ==
  
== Preparing for J-Link ==
Line 10: Line 10:
 
! J-Link Pin || Connector !! Pin || Name
  
! J-Link Pin || Connector !! Pin || Name
 
|-
  
|-
−
| VTref || J1 || 72 || VDD
 +
| VTref || J1 || 23 || VDD
 
|-
  
|-
−
| GND || J1 || 71 || GND
 +
| GND || J1 || 22 || GND
 
|-
  
|-
−
| TDI || J1 || 71 || GND
 +
| TDI || J1 || 25 || PA15
 
|-
  
|-
−
| TMS/SWDIO || J1 || 33 || PA13/SWDIO
 +
| TMS/SWDIO || J1 || 20|| PA13
 
|-
  
|-
−
| TCK/SWCLK || J1 || 37 || PA14/SWCLK
 +
| TCK/SWCLK || J1 || 24 || PA14
 
|-
  
|-
−
| TDO/SWO || J1 || 61 || PB3
 +
| TDO/SWO || J1 || 37|| PB3
 
|-
  
|-
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| RESET || J1 || 25 || NRST
 +
| RESET || J2 || 14 || NRST
 
|}
  
|}
 
*Power the board via CN4.
  
*Power the board via CN4.
 
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
  
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
−
[[File:Artery_AT-START-F403_AT32F403AVGT7_connect.png|400px]]
 +
[[File:Artery_AT-START-F403A_AT32F403AVGT7_connect.png|400px]]
   
 
== Example Project==
  
== Example Project==
−
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F413.<br>
 +
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F403A.<br>
 
It is a simple Hello World sample linked into the internal flash.<br>
  
It is a simple Hello World sample linked into the internal flash.<br>
 
====SETUP====
  
====SETUP====
−
*J-Link software: V7.94i
 +
*J-Link software: V7.94j
 
*Embedded Studio: V7.20
  
*Embedded Studio: V7.20
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*Hardware: Artery AT-START-F413
 +
*Hardware: ArteryTek AT-START-F403A
−
*Link: [[File:Artery_AT-START-F403_AT32F403AVGT7_TestProject_ES_7V20.zip]]
 +
*Link: [[File:Artery_AT-START-F403A_AT32F403AVGT7_TestProject_ES_7V20.zip]]

Latest revision as of 16:32, 8 February 2024

This article describes specifics for the ArteryTek AT-START-F403A evaluation board.
Artery AT-START-F403A AT32F403AVGT7 board.jpg

Preparing for J-Link

  • Connect the J-Link to this pins:
J-Link Pin Connector Pin Name
VTref J1 23 VDD
GND J1 22 GND
TDI J1 25 PA15
TMS/SWDIO J1 20 PA13
TCK/SWCLK J1 24 PA14
TDO/SWO J1 37 PB3
RESET J2 14 NRST
  • Power the board via CN4.
  • Verify the Connection with e.g. J-Link Commander. The output should look as follows:

Artery AT-START-F403A AT32F403AVGT7 connect.png

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F403A.
It is a simple Hello World sample linked into the internal flash.

SETUP

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