ArteryTek AT-START-F403A
Revision as of 15:34, 7 February 2024 by Torben.scharping (talk | contribs) (Created page with "__TOC__ This article describes specifics for the Artery AT-START-F403 evaluation board.<br> 450px == Preparing for J-Li...")
This article describes specifics for the Artery AT-START-F403 evaluation board.
450px
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 72 | VDD |
| GND | J1 | 71 | GND |
| TDI | J1 | 71 | GND |
| TMS/SWDIO | J1 | 33 | PA13/SWDIO |
| TCK/SWCLK | J1 | 37 | PA14/SWCLK |
| TDO/SWO | J1 | 61 | PB3 |
| RESET | J1 | 25 | NRST |
- Power the board via CN4.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F413.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94i
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F413
- Link: File:Artery AT-START-F403 AT32F403AVGT7 TestProject ES 7V20.zip
