Difference between revisions of "ArteryTek AT-START-F407"
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*Power the board via CN4. |
*Power the board via CN4. |
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* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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| − | [[File:Artery_AT |
+ | [[File:Artery_AT-START-F407_AT32F407VGT7_connect.png|400px]] |
== Example Project== |
== Example Project== |
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Revision as of 10:19, 8 February 2024
This article describes specifics for the Artery AT-START-F407 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 23 | VDD |
| GND | J1 | 22 | GND |
| TDI | J1 | 25 | PA15 |
| TMS/SWDIO | J1 | 20 | PA13 |
| TCK/SWCLK | J1 | 24 | PA14 |
| TDO/SWO | J1 | 37 | PB3 |
| RESET | J2 | 14 | NRST |
- Power the board via CN4.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F407.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94j
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F407
- Link: File:Artery AT-START-F407 AT32F407VGT7 TestProject ES 7V20.zip
