Difference between revisions of "ArteryTek AT-START-F413"
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− | This article describes specifics for the |
+ | This article describes specifics for the ArteryTek AT-START-F413 evaluation board.<br> |
[[File:Artery_AT-START-F413_AT32F413RCT7_board.jpg|450px]] |
[[File:Artery_AT-START-F413_AT32F413RCT7_board.jpg|450px]] |
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== Example Project== |
== Example Project== |
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− | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the |
+ | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F413.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
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====SETUP==== |
====SETUP==== |
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− | *J-Link software: V7. |
+ | *J-Link software: V7.94i |
*Embedded Studio: V7.20 |
*Embedded Studio: V7.20 |
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− | *Hardware: |
+ | *Hardware: ArteryTek AT-START-F413 |
− | *Link: [[File:Artery_AT |
+ | *Link: [[File:Artery_AT-START-F413_AT32F413RCT7_TestProject_ES_7V20.zip]] |
Latest revision as of 16:36, 8 February 2024
This article describes specifics for the ArteryTek AT-START-F413 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 72 | VDD |
GND | J1 | 71 | GND |
TDI | J1 | 71 | GND |
TMS/SWDIO | J1 | 33 | PA13/SWDIO |
TCK/SWCLK | J1 | 37 | PA14/SWCLK |
TDO/SWO | J1 | 61 | PB3 |
RESET | J1 | 25 | NRST |
- Power the board via CN4.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F413.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94i
- Embedded Studio: V7.20
- Hardware: ArteryTek AT-START-F413
- Link: File:Artery AT-START-F413 AT32F413RCT7 TestProject ES 7V20.zip