Difference between revisions of "ArteryTek AT-START-F415"
(Created page with "__TOC__ This article describes specifics for the Artery AT-START-F415 evaluation board.<br> 450px == Preparing for J-Li...") |
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__TOC__ |
__TOC__ |
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| − | This article describes specifics for the |
+ | This article describes specifics for the ArteryTek AT-START-F415 evaluation board.<br> |
[[File:Artery_AT-START-F415_AT32F415RCT7-7_board.jpg|450px]] |
[[File:Artery_AT-START-F415_AT32F415RCT7-7_board.jpg|450px]] |
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| Line 13: | Line 13: | ||
| GND || J1 || 31 || GND |
| GND || J1 || 31 || GND |
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| − | | |
+ | | TDI || J1 || 18|| PA15 |
|- |
|- |
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| − | | |
+ | | TMS/SWDIO || J1 || 14 || PA13 |
| + | |- |
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| + | | TCK/SWCLK || J1 || 17 || PA14 |
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|- |
|- |
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| TDO/SWO || J1 || 23 || PB3 |
| TDO/SWO || J1 || 23 || PB3 |
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| Line 21: | Line 23: | ||
| RESET || J2 || 7 || NRST |
| RESET || J2 || 7 || NRST |
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| − | *Power the board via USB |
+ | *Power the board via USB CN6. |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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[[File:Artery_AT-START-F415_AT32F415RCT7-7_connect.png|400px]] |
[[File:Artery_AT-START-F415_AT32F415RCT7-7_connect.png|400px]] |
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== Example Project== |
== Example Project== |
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| − | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the |
+ | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F415.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
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====SETUP==== |
====SETUP==== |
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| − | *J-Link software: V7. |
+ | *J-Link software: V7.94h |
*Embedded Studio: V7.20 |
*Embedded Studio: V7.20 |
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| − | *Hardware: |
+ | *Hardware: ArteryTek AT-START-F415 |
*Link: [[File:Artery_AT-START-F415_AT32F415RCT7-7_TestProject_ES_7V20.zip]] |
*Link: [[File:Artery_AT-START-F415_AT32F415RCT7-7_TestProject_ES_7V20.zip]] |
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Latest revision as of 16:37, 8 February 2024
This article describes specifics for the ArteryTek AT-START-F415 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 32 | VDD |
| GND | J1 | 31 | GND |
| TDI | J1 | 18 | PA15 |
| TMS/SWDIO | J1 | 14 | PA13 |
| TCK/SWCLK | J1 | 17 | PA14 |
| TDO/SWO | J1 | 23 | PB3 |
| RESET | J2 | 7 | NRST |
- Power the board via USB CN6.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F415.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94h
- Embedded Studio: V7.20
- Hardware: ArteryTek AT-START-F415
- Link: File:Artery AT-START-F415 AT32F415RCT7-7 TestProject ES 7V20.zip
