Difference between revisions of "ArteryTek AT-START-F423"

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(Preparing for J-Link)
Line 9: Line 9:
 
! J-Link Pin || Connector !! Pin || Name
 
! J-Link Pin || Connector !! Pin || Name
 
|-
 
|-
| VTref || J1 || 24|| VDD
+
| VTref || J1 || 50|| VDD
 
|-
 
|-
| GND || J1 || 23 || GND
+
| GND || J1 || 49 || GND
 
|-
 
|-
| SWDIO || J1 || 10 || PA13
+
| TMS/SWDIO || J1 || 20 || PA13/SWDIO
 
|-
 
|-
| SWCLK || J1 || 13 || PA14
+
| TCK/SWCLK || J1 || 24 || PA14/SWCLK
 
|-
 
|-
| RESET || J2 || 7 || NRST
+
| TDO/SWO || J1 || 39 || PB3/SWO
  +
|-
  +
| RESET || J2 || 14 || NRST
 
|}
 
|}
*Power the board via CH4.
+
*Power the board via CN5.
 
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
 
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
 
[[File:Artery_AT-START-F423_AT32F423VCT7_connect.png|400px]]
 
[[File:Artery_AT-START-F423_AT32F423VCT7_connect.png|400px]]

Revision as of 10:37, 23 January 2024

This article describes specifics for the Artery AT-START-F423 evaluation board.
Artery AT-START-F423 AT32F423VCT7 board.jpg

Preparing for J-Link

  • Connect the J-Link to this pins:
J-Link Pin Connector Pin Name
VTref J1 50 VDD
GND J1 49 GND
TMS/SWDIO J1 20 PA13/SWDIO
TCK/SWCLK J1 24 PA14/SWCLK
TDO/SWO J1 39 PB3/SWO
RESET J2 14 NRST
  • Power the board via CN5.
  • Verify the Connection with e.g. J-Link Commander. The output should look as follows:

Artery AT-START-F423 AT32F423VCT7 connect.png

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F423.
It is a simple Hello World sample linked into the internal flash.

SETUP