Difference between revisions of "ArteryTek AT-START-F423"
(→Preparing for J-Link) |
(→Preparing for J-Link) |
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| Line 13: | Line 13: | ||
| GND || J1 || 49 || GND |
| GND || J1 || 49 || GND |
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| − | | TDI || J1 || 20 || |
+ | | TDI || J1 || 20 || PA15 |
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| TMS/SWDIO || J1 || 20 || PA13/SWDIO |
| TMS/SWDIO || J1 || 20 || PA13/SWDIO |
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| Line 19: | Line 19: | ||
| TCK/SWCLK || J1 || 24 || PA14/SWCLK |
| TCK/SWCLK || J1 || 24 || PA14/SWCLK |
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|- |
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| − | | TDO/SWO || J1 || 39 || PB3 |
+ | | TDO/SWO || J1 || 39 || PB3 |
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| RESET || J2 || 14 || NRST |
| RESET || J2 || 14 || NRST |
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Revision as of 09:34, 24 January 2024
This article describes specifics for the Artery AT-START-F423 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 50 | VDD |
| GND | J1 | 49 | GND |
| TDI | J1 | 20 | PA15 |
| TMS/SWDIO | J1 | 20 | PA13/SWDIO |
| TCK/SWCLK | J1 | 24 | PA14/SWCLK |
| TDO/SWO | J1 | 39 | PB3 |
| RESET | J2 | 14 | NRST |
- Power the board via CN5.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F423.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94g
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F423
- Link: File:Artery AT-START-F423 AT32F423VCT7 TestProject ES 7V20.zip
