Difference between revisions of "ArteryTek AT-START-F423"
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It is a simple Hello World sample linked into the internal flash.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
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====SETUP==== |
====SETUP==== |
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− | *J-Link software: V7. |
+ | *J-Link software: V7.94i |
*Embedded Studio: V7.20 |
*Embedded Studio: V7.20 |
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*Hardware: Artery AT-START-F423 |
*Hardware: Artery AT-START-F423 |
Revision as of 12:01, 1 February 2024
This article describes specifics for the Artery AT-START-F423 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 50 | VDD |
GND | J1 | 49 | GND |
TDI | J1 | 20 | PA15 |
TMS/SWDIO | J1 | 20 | PA13/SWDIO |
TCK/SWCLK | J1 | 24 | PA14/SWCLK |
TDO/SWO | J1 | 39 | PB3 |
RESET | J2 | 14 | NRST |
- Power the board via CN5.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F423.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94i
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F423
- Link: File:Artery AT-START-F423 AT32F423VCT7 TestProject ES 7V20.zip