Difference between revisions of "ArteryTek AT-START-F423"
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− | This article describes specifics for the |
+ | This article describes specifics for the ArteryTek AT-START-F423 evaluation board.<br> |
[[File:Artery_AT-START-F423_AT32F423VCT7_board.jpg|450px]] |
[[File:Artery_AT-START-F423_AT32F423VCT7_board.jpg|450px]] |
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! J-Link Pin || Connector !! Pin || Name |
! J-Link Pin || Connector !! Pin || Name |
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|- |
|- |
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− | | VTref || J1 || |
+ | | VTref || J1 || 50|| VDD |
|- |
|- |
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− | | GND || J1 || |
+ | | GND || J1 || 49 || GND |
|- |
|- |
||
− | | |
+ | | TDI || J1 || 20 || PA15 |
|- |
|- |
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− | | |
+ | | TMS/SWDIO || J1 || 20 || PA13/SWDIO |
|- |
|- |
||
− | | |
+ | | TCK/SWCLK || J1 || 24 || PA14/SWCLK |
+ | |- |
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+ | | TDO/SWO || J1 || 39 || PB3 |
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+ | |- |
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+ | | RESET || J2 || 14 || NRST |
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|} |
|} |
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− | *Power the board via |
+ | *Power the board via CN5. |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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[[File:Artery_AT-START-F423_AT32F423VCT7_connect.png|400px]] |
[[File:Artery_AT-START-F423_AT32F423VCT7_connect.png|400px]] |
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== Example Project== |
== Example Project== |
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− | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the |
+ | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F423.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
It is a simple Hello World sample linked into the internal flash.<br> |
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====SETUP==== |
====SETUP==== |
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− | *J-Link software: V7. |
+ | *J-Link software: V7.94i |
*Embedded Studio: V7.20 |
*Embedded Studio: V7.20 |
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− | *Hardware: |
+ | *Hardware: ArteryTek AT-START-F423 |
*Link: [[File:Artery_AT-START-F423_AT32F423VCT7_TestProject_ES_7V20.zip]] |
*Link: [[File:Artery_AT-START-F423_AT32F423VCT7_TestProject_ES_7V20.zip]] |
Latest revision as of 16:38, 8 February 2024
This article describes specifics for the ArteryTek AT-START-F423 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 50 | VDD |
GND | J1 | 49 | GND |
TDI | J1 | 20 | PA15 |
TMS/SWDIO | J1 | 20 | PA13/SWDIO |
TCK/SWCLK | J1 | 24 | PA14/SWCLK |
TDO/SWO | J1 | 39 | PB3 |
RESET | J2 | 14 | NRST |
- Power the board via CN5.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ArteryTek AT-START-F423.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94i
- Embedded Studio: V7.20
- Hardware: ArteryTek AT-START-F423
- Link: File:Artery AT-START-F423 AT32F423VCT7 TestProject ES 7V20.zip