Difference between revisions of "ArteryTek AT-START-F437"
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| − | This article describes specifics for the |
+ | This article describes specifics for the Artery AT-START-F437 evaluation board.<br> |
'''[PICTURE OF BOARD]''' |
'''[PICTURE OF BOARD]''' |
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[[File:VENDOR_BOARDNAME.jpg|450px]] |
[[File:VENDOR_BOARDNAME.jpg|450px]] |
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== Preparing for J-Link == |
== Preparing for J-Link == |
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| − | *Connect the J-Link to ...... |
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*Connect the J-Link to this pins: |
*Connect the J-Link to this pins: |
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{| class="seggertable" |
{| class="seggertable" |
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| Line 12: | Line 11: | ||
! J-Link Pin || Connector !! Pin || Name |
! J-Link Pin || Connector !! Pin || Name |
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|- |
|- |
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| − | | VTref || || || |
+ | | VTref || J1 || 72 || VDD |
|- |
|- |
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| − | | GND || || || |
+ | | GND || J1 || 71 || GND |
|- |
|- |
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| − | | |
+ | | TMS/SWDIO || J1 || 33 || PA13/SWDIO |
|- |
|- |
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| − | | |
+ | | TCK/SWCLK || J1 || 37 || PA14/SWCLK |
|- |
|- |
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| − | | |
+ | | TDO/SWO || J1 || 61 || PB3 |
|- |
|- |
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| − | | |
+ | | RESET || J1 || 25 || NRST |
| − | |- |
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| − | | RTCK || || || |
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| − | |- |
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| − | | TDO/SWO || || || |
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| − | |- |
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| − | | RESET || || || |
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| − | |- |
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| − | | DBGRQ || || || |
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| − | |- |
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| − | | 5V-Supply || || || |
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| − | |||
|} |
|} |
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| − | *Power the board via |
+ | *Power the board via USB (CN2 or CN3). |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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'''[PICTURE OF CONNECT]''' |
'''[PICTURE OF CONNECT]''' |
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Revision as of 11:55, 18 January 2024
This article describes specifics for the Artery AT-START-F437 evaluation board.
[PICTURE OF BOARD]
450px
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 72 | VDD |
| GND | J1 | 71 | GND |
| TMS/SWDIO | J1 | 33 | PA13/SWDIO |
| TCK/SWCLK | J1 | 37 | PA14/SWCLK |
| TDO/SWO | J1 | 61 | PB3 |
| RESET | J1 | 25 | NRST |
- Power the board via USB (CN2 or CN3).
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
[PICTURE OF CONNECT]
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the [SiliconVendor] [EvalBoardName].
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.xx
- Embedded Studio: V7.20
- Hardware: [SiliconVendor] [EvalBoardName]
- Link: File:VENDOR DEVICENAME TestProject ES V452b.zip
