Difference between revisions of "ArteryTek AT-START-F437"
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*Embedded Studio: V7.20 |
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*Hardware: Artery AT-START-F437 |
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| − | *Link: [[File: |
+ | *Link: [[File:Artery_AT-START-F437_AT32F437ZMT7_TestProject_ES_7V20.zip]] |
Revision as of 12:42, 18 January 2024
This article describes specifics for the Artery AT-START-F437 evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 72 | VDD |
| GND | J1 | 71 | GND |
| TMS/SWDIO | J1 | 33 | PA13/SWDIO |
| TCK/SWCLK | J1 | 37 | PA14/SWCLK |
| TDO/SWO | J1 | 61 | PB3 |
| RESET | J1 | 25 | NRST |
- Power the board via USB (CN2 or CN3).
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F437.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94g
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F437
- Link: File:Artery AT-START-F437 AT32F437ZMT7 TestProject ES 7V20.zip
