ArteryTek AT-START-F437
Revision as of 11:55, 18 January 2024 by Torben.scharping (talk | contribs)
This article describes specifics for the Artery AT-START-F437 evaluation board.
[PICTURE OF BOARD]
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Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J1 | 72 | VDD |
GND | J1 | 71 | GND |
TMS/SWDIO | J1 | 33 | PA13/SWDIO |
TCK/SWCLK | J1 | 37 | PA14/SWCLK |
TDO/SWO | J1 | 61 | PB3 |
RESET | J1 | 25 | NRST |
- Power the board via USB (CN2 or CN3).
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the [SiliconVendor] [EvalBoardName].
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.xx
- Embedded Studio: V7.20
- Hardware: [SiliconVendor] [EvalBoardName]
- Link: File:VENDOR DEVICENAME TestProject ES V452b.zip