Difference between revisions of "ArteryTek AT32A40x"
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==Device Specific Handling== |
==Device Specific Handling== |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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| + | |||
===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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Revision as of 10:18, 16 March 2024
ArteryTek AT32A40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | 1024KB | 
|
| User data | 0x1FFFF800 | 512B |
|
| SPIM external flash | 0x08400000 | 16 MB |
|
Notes for use of SPIM external flash
- For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming.
- Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now.
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
